Control network generator for latency insensitive designs

Abstract

Abstract-Creating latency insensitive or asynchronous designs from clocked designs has potential benefits of increased modularity and robustness to variations. Several transformations have been suggested in the literature and each of these require a handshake control network (examples include synchronous elasticization and desynchronization). Numerous implementations of the control network are possible. This paper reports on an algorithm that has been proven to generate an optimal control network consisting of the minimum number of 2-input join and 2-output fork control components. This can substantially reduce the area and power consumption of a system. The algorithm has been implemented in a CAD tool, called CNG. It has been applied to the MiniMIPS processor showing a 14% reduction in the number of control steering units over a hand optimized design in a contemporary work.

Design and Verification of Lazy and Hybrid Implementations of the SELF Protocol

“…18 but with two fewer joins and two fewer forks. It is auto-generated by the CN G tool, a tool that given the required register-to-register communications will automatically generate a control network with the minimum total number of joins and forks [11]. Furthermore, we insert zero to three bubbles (i.e., EBs that hold no valid data) at the register file output (i.e., at the inputs of A and B registers simultaneously).…”

“…9. Starting with an elastic control network (generated manually or through automatic tools like CN G [11]), the following flow generates a hybrid SELF implementation (H) of that network:…”

“…Hence, minimizing these overheads is a primary concern. For an attempt to achieve that goal, an algorithm that minimizes the total number of control steering units (i.e., joins and forks) in the LI control network has been developed [11].…”

Synchronous elasticization at a reduced cost: Utilizing the ultra simple fork and controller merging

“…For the sake of comparison, we use the case study elasticized by the authors of [9] and [8], MiniMIPS. The MiniMIPS is an 8-bit subset of the 32-bit MIPS (Microprocessor without Interlocked Pipeline Stages) [15], [16].…”

“…Therefore, minimizing these overheads is a primary concern. An algorithm that minimizes the total number of control steering units (i.e., joins and forks) in the LI control network (and, hence, its area and power overheads) has been proposed in [9]. Due to its lower area and power overheads, lazy SELF implementation can become an attractive solution.…”