Control-enhanced power-SIMD

Decoupled iteration mapping: improving dependency-loop performance on SIMD processors

“…Area consumption is measured using the RTL Verilog model of the prototype YHFT Matrix DSP [6] and synthesized using typical operation conditions in TSMC 45 nm technology target at 1 GHz. The total area of DSP is 12 mm Table I, normalized with respect to the "Original" version.…”

“…2 (a) . We have introduced the first two parts in the previous research [6]. In this paper we emphasize the third part, DBC, a dedicated hardware structure for pipelined inter-thread communication.…”

Divergent Branch Threads Compaction for Efficient SIMD Control Flow

“…To verify the hardware cost of DBTC mode architecture, we add four major parts to the hardware implementation of the prototype YHFT-matrix processor [11] in Verilog HDL. The prototype contains a scalar control unit, 16 VPEs each with 4 function units, 1MB VM, and 16KB of Instruction cache.…”

“…We have implemented a selection of a set of representative irregular applications to illustrate the key feature of the new architecture, including examples from the EEMBC benchmark suit and applications from the H.264/AVC high definition real-time video compression, as well as two implementations of applications in computer arithmetic that exhibit highly irregular control flow, Table 4 shows the mapping results and the description of the representative applications in DBTC mode. We model our proposed hardware changes using a cycle-accurate modified version of FT-Matrix-sim [11] , and manually optimized assemble code is used as the input of the simulator.…”

“…In all, the depth should be determined to the specific applications. It should be mentioned that the proposed hardware mechanism can be used to support software pipeline [11] and accelerate loop depended code [12] , which explores the potential variable type parallelism. However, the instruction shuffle [10] is very limited and lakes flexible.…”