Control and datapath decoupling in the design of a NoC switch: area, power and performance implications

Medardoni, Simone; Bertozzi, Davide; Benini, Luca; Macii, Enrico

doi:10.1109/issoc.2007.4427438

Cited by 6 publications

(10 citation statements)

References 15 publications

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“…In principle, this might lead to an increased communication latency through the network, but a lack of output latching might give rise to long signal paths degrading global design performance. Circuitswitching architectures like the one reported in [16] are ideal candidate for our self-correcting FFs, since they implement end-to-end flow control and feature retiming stages at switch inputs and outputs. Finally, our technique applies to output-buffered switches as well with a few modifications.…”

Section: Applicabilitymentioning

confidence: 99%

Variation tolerant NoC design by means of self-calibrating links

Simone¹,

Lajolo²,

Bertozzi³

2008

2008 Design, Automation and Test in Europe

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We present the implementation and analysis of a variation tolerant version of a switch-to-switch link in a NoC. The goal is to tolerate the effects of process variations on NoC architectures using self-correcting links that automatically detect delay variations and compensate them. The correction is applied without increasing the switch-to-switch latency by substituting the output flip-flops of the sending switch with a self-correcting flip-flop followed by an adaptive voltage swing selector. Higher delay variations will result in a smaller slack in the switch-to-switch path, but the adaptive voltage swing selector could mitigate its impact on the NoC communication by increasing the voltage swing on the link, thus allowing a compensation of the delay variation. As a result, it is possible to tolerate delay variations at the cost of additional power consumption

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Section: Applicabilitymentioning

confidence: 99%

Variation tolerant NoC design by means of self-calibrating links

Simone¹,

Lajolo²,

Bertozzi³

2008

2008 Design, Automation and Test in Europe

Self Cite

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“…Some recent works [13,14,16] show that, as the switch buffer size is decreased, the clock frequency can be increased. In particular, by eliminating the buffers at the switch ports and replacing them by one-flit latches, the switch frequency can be increased from 1GHz up to more than 2GHz [13,14].…”

Section: Motivationmentioning

confidence: 99%

“…In particular, by eliminating the buffers at the switch ports and replacing them by one-flit latches, the switch frequency can be increased from 1GHz up to more than 2GHz [13,14]. Decoupling the control logic from the switch data-path, leads to reduce the critical path by a 52% [14].…”

Section: Motivationmentioning

confidence: 99%

“…Decoupling the control logic from the switch data-path, leads to reduce the critical path by a 52% [14]. Moreover, even increasing the crossbar size, a 59% of the switch delay is due to the buffers and the flow control logic [14]. Therefore, switch critical path can be reduced by removing or reducing the switch port buffers, since the buffering architecture at the switch ports requires some control logic whose delay adds up to data-path delay, thus limiting the clock frequency.…”

Section: Motivationmentioning

confidence: 99%

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An Efficient Switching Technique for NoCs with Reduced Buffer Requirements

Gómez¹,

Gómez²,

López³

et al. 2008

2008 14th IEEE International Conference on Parallel and Distributed Systems

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Networks on chip (NoCs) communicate the components located inside a chip. Overall system performance depends on NoC performance, that is affected by several factors. One of them is the network clock frequency, imposed by the critical path delay. Recent works show that switch critical path includes buffer control logic. Consequently, by removing switch buffers, switch frequency can be doubled. In this paper, we exploit this idea, proposing a new switching technique for NoCs which requires a reduced amount of storage at the switches. It is based on replacing switch port buffers by single latches. By doing so, network cycle can be reduced, which reduces packet latency. On the other hand, power and area consumption requirements can be reduced. However, since there are no buffers at the switch ports, packets can not be stopped. Stopped packets due to contention are dropped and reinjected from their senders via negative acknowledgments. Packet dropping is strongly reduced by exploiting NoCs wiring capability.

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“…A lot of works have been made in order to reduce the costs of the interconnection network for off-chip interconnection networks [17,62,68,119] and for NoCs [22,51,53,87,107,132]. Some of these works rely on developing mechanism that dynamically can switch on and off the links of the interconnection network [17], or adjusting the working frequency or voltage of the system [53,119], or reducing the amount of memory at the switches [62], or designing new flow-control mechanisms [107], and many other changes on the structure of the elements of the network.…”

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confidence: 99%

Low-Memory Techniques for Routing and Fault-Tolerance on the Fat-Tree Topology

Requena¹

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Control and datapath decoupling in the design of a NoC switch: area, power and performance implications

Cited by 6 publications

References 15 publications

Variation tolerant NoC design by means of self-calibrating links

Variation tolerant NoC design by means of self-calibrating links

An Efficient Switching Technique for NoCs with Reduced Buffer Requirements

Low-Memory Techniques for Routing and Fault-Tolerance on the Fat-Tree Topology

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