Contribution to the modeling of a non-ideal Sigma-Delta modulator

Dendouga, Abdelghani; Bouguechal, Nour-Eddine; Kouda, Souhil; Barra, Samir; Lakehal, Brahim

doi:10.1007/s10825-012-0409-8

Cited by 11 publications

(5 citation statements)

References 7 publications

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“…Integral Non-Linearity Error (INLE) The aim of INL and DNL modeling is to change the transition code length moves the ideal transfer function [4]. The mean value is for INL and the range of uniformly random source is for DNL.…”

Section: E Differential Non-linearity Error (Dnle) Andmentioning

confidence: 99%

“…Mathematically the clock jitter of a sampled signal is given by (13) δ is the deviation in sampling time, is resultant error due to clock jitter with as the sampling time. Using Taylor's series expression (13) can be expanded as (14) The effect of clock jitter leads to non-uniform sequence of samples [4]. This increases the error at the Power spectral density of pipeline ADC as shown in fig.…”

Section: Fig 4 Output Characteristics Of Sample and Hold Circuit Dmentioning

confidence: 99%

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Design and Performance Evaluation of Ideal and Non-Ideal Effects of Pipeline ADC using Software Reference Models

B*¹,

Meshram²

2019

IJRTE

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Analog-to-digital converter (ADC) is one of the key component in any of the application oriented system design. This paper mainly focused on the simulation of various non-ideal parameters of an ADC as the number of resolution increases. The effect of non-ideal aspects like Jitter model and error block model are created in Matlab Simulink and the results are plotted. The dynamic non-ideal characteristics are discussed with their mathematical models and are compared with the equivalent resolution ADCs. The preliminary observations are also drawn according to the ideal characteristics. This shows that as the resolution increases, the bandwidth of non-ideal characteristics are also increases. This work is entitled to prove the non-idealities of 12-bit Pipeline ADC.

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Section: E Differential Non-linearity Error (Dnle) Andmentioning

confidence: 99%

Section: Fig 4 Output Characteristics Of Sample and Hold Circuit Dmentioning

confidence: 99%

Design and Performance Evaluation of Ideal and Non-Ideal Effects of Pipeline ADC using Software Reference Models

B*¹,

Meshram²

2019

IJRTE

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“…This clock jitter can be understood from Figure 14, in which the sampling uncertainty δ is a Gaussian random process with standard deviation of Δ t . 1,17 When a sinusoidal signal x ( t ) with amplitude A and frequency f is sampled at an instant having a deviation of δ , the clock jitter error is given by the following 18 :…”

Section: Proposed Auto-configurable Successive Approximation Regismentioning

confidence: 99%

Modeling and simulation of an eight-bit auto-configurable successive approximation register analog-to-digital converter for cardiac and neural implants

Ahmed

Kakkar

2017

SIMULATION

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An analog-to-digital converter (ADC) is a critical block of the sensing unit of all implants and for measurements of various biophysiological signals that cover distinct portions of the frequency spectrum and signal bandwidths. However, the conventional methodology of direct transistor-level implementation of the ADC for any application does not guarantee the accuracy to meet the desired specifications. For this purpose, the behavioral modeling approach facilitates the designer to set up an environment to extract various electric and dynamic parameters with a good level of accuracy. Based on this, behavioral modeling of a new architecture of an eight-bit auto-configurable successive approximation register (SAR) ADC has been proposed in this paper for application in both cardiac and neural implants, such as pacemakers, deep brain stimulators, etc. All the building blocks of the SAR ADC have been modeled in such a way that the ADC can operate either in the voltage mode or the current mode and the various non-idealities, such as clock jitter, clock feedthrough, and thermal and flicker noise, among others, have been incorporated into the design to make it as realistic as possible and estimate the response of the ADC with high accuracy. Based on the simulations for both ideal and non-ideal scenarios, it is observed that the proposed eight-bit auto-configurable SAR ADC works efficiently for applications in both cardiac and neural implants and achieves a signal-to-noise ratio as high as 48.943 dB and effective number of bits of 7.838 bits with very low distortion of only-62.549 dB.

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“…where i is the stage number and N is the number of bits. Inequality (20) shows that the capacitor mismatch error is low in the front-end, but it is superior in the higher stage resolutions.…”

Section: Capacitor Mismatch Errorsmentioning

confidence: 99%

“…13. This error is introduced when a sinusoidal signal x(t) with amplitude A and frequency fin is sampled at an instant which is in error by an amount δ and is given by [20] . Here, we assumed that the sampling uncertainty δ is a Gaussian random process with a standard deviation ∆τ [19] .…”

Section: Clock Jittermentioning

confidence: 99%

Simulink Behavioral Modeling of a 10- bit Pipelined ADC

Barra

Kouda

Dendouga

et al. 2013

Int. J. Autom. Comput.

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The increasing architecture complexity of data converters makes it necessary to use behavioral models to simulate their electrical performance and to determine their relevant data features. For this purpose, a specific data converter simulation environment has been developed which allows designers to perform time-domain behavioral simulations of pipelined analog to digital converters (ADCs). All the necessary blocks of this specific simulation environment have been implemented using the popular Matlab simulink environment. The purpose of this paper is to present the behavioral models of these blocks taking into account most of the pipelined ADC non-idealities, such as sampling jitter, noise, and operational amplifier parameters (white noise, finite DC gain, finite bandwidth, slew rate, and saturation voltages). Simulations, using a 10-bit pipelined ADC as a design example, show that in addition to the limits analysis and the electrical features extraction, designers can determine the specifications of the basic blocks in order to meet the given data converter requirements.

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Contribution to the modeling of a non-ideal Sigma-Delta modulator

Cited by 11 publications

References 7 publications

Design and Performance Evaluation of Ideal and Non-Ideal Effects of Pipeline ADC using Software Reference Models

Design and Performance Evaluation of Ideal and Non-Ideal Effects of Pipeline ADC using Software Reference Models

Modeling and simulation of an eight-bit auto-configurable successive approximation register analog-to-digital converter for cardiac and neural implants

Simulink Behavioral Modeling of a 10- bit Pipelined ADC

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