CONTRIBUTION TO THE ANALYSIS AND MODELING OF THE NON-IDEAL EFFECTS OF PIPELINED ADCs USING MATLAB

Abstract

The present work analyses the non-ideal effects of pipelined analog-to-digital converters (ADCs), also sometimes referred to as pipeline ADCs, including the non-ideal effects in operational amplifiers (op-amps or OAs), switches and sampling circuits. We study these nonlinear effects in pipelined ADCs built using CMOS technology and switched-capacitor (SC) techniques. The proposed improved model of a pipelined ADC includes most of the non-idealities which affect its performance. This model, simulated using MATLAB, can determine the basic blocks specifications that allow the designer to meet given data converter requirements.

Design and Performance Evaluation of Ideal and Non-Ideal Effects of Pipeline ADC using Software Reference Models

“…The thermal noise is one of the main noise for high speed sample and hold circuit. The noise density is: (11) Combination of the transfer function (9), the output noise is: In order to decrease the noise impact, to increase the , but the expression (10) shows that the increasing of sample capacitance will leads to a time limit in bandwidth. To ensure the bandwidth increase the size of switch transistor this reduces the conduction resistance [1].…”

“…The design is for 12-bit resolution to convert digital to analog and analog to digital. The each step having an effect with clock jitter which will affect the signal accuracy [11]. The proposed work introduces the pipeline ADC model developed using MATLAB Simulink.…”

Behavioral non-ideal Model of 8-bit Current-Mode Successive Approximation Registers ADC by using Simulink

“…This uncertainty Δt the sampling instant, commonly called jitter, this non-ideal factor produces a conversion error proportional to the slope of the signal; The error result from clock jitter can be expressed as [15] (05)…”

Simulink Behavioral Modeling of a 10- bit Pipelined ADC

“…Jitter error can be reduced by oversampling the input signal. The clock jitter value of a sampled signal is represented as [19] x…”

“…where x i (t) is the error due to the jitter deviation of δ in sample value xi(t) with a true sampling frequency fs. Using Taylor s series expansion, we have [19] δ…”