Contribution of EUV resist counting statistics to stochastic printing failures

Hinsberg, William D.; Wallraff, Gregory M.; Sanchez, Martha I.; Megiddo, Nimrod; Kostko, Oleg

doi:10.1117/1.jmm.20.1.014603

Cited by 7 publications

(6 citation statements)

References 40 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…When photoacid generators (PAGs) are not bonded to the resist polymers, PAG-PAG spacings will be variable. For a resist with high PAG loading, the average PAG-PAG spacing is 1.7 nm, 31,32) which sets the scale for roughness. Variation in component spacings can be increased beyond that expected from pure randomness due to the phenomena of segregation and aggregation.…”

Section: Resists Meeting Resolution Requirementsmentioning

confidence: 99%

High-NA EUV lithography: current status and outlook for the future

Levinson¹

2022

Jpn. J. Appl. Phys.

View full text Add to dashboard Cite

High-NA extreme ultraviolet (EUV) lithography is currently in development. Fabrication of exposure tools and optics with a numerical aperture (NA) equal to 0.55 has started at ASML and Carl Zeiss. Lenses with such high NA will have very small depths-of-focus, which will require improved focus systems and significant improvements in wafer flatness during processing. Lenses are anamorphic to address mask 3D issues, which results in wafer field sizes of 26 mm × 16.5 mm, half that of lower NA EUV tools and optical scanners. Production of large die will require stitching. Computational infrastructure is being created to support high-NA lithography, including simulators that use Tatian polynomials to characterize the aberrations of lenses with central obscurations. High resolution resists that meet the line-edge roughness (LER) and defect requirements for high-volume manufacturing (HVM) also need to be developed. High power light sources will also be needed to limit photon shot noise.

show abstract

Section: Resists Meeting Resolution Requirementsmentioning

confidence: 99%

High-NA EUV lithography: current status and outlook for the future

Levinson¹

2022

Jpn. J. Appl. Phys.

View full text Add to dashboard Cite

show abstract

“…The parameters in this model are set to image 22 nm features using 0.55 NA illumination. To facilitate the study of defectivity, the suppressed resist defect is approximately 10 6 times greater than a minimally acceptable 10 defects per cm 2 . This increased defectivity rate produces less than 2:20 000 defects in the stochastic target case for an approximately 100 nm by 100 nm simulated region with no other perturbations.…”

Section: Process Modelmentioning

confidence: 99%

“…There have been many literature studies 1,2) of stochastic defectivity in laboratory EUV exposure processes. These studies were critical to provide understanding, and a modeling foundation for this defectivity type.…”

Section: Introductionmentioning

confidence: 99%

Applying stochastic simulation to study defect formation in EUV photoresists

Melvin

Welling

Kandel

et al. 2022

Jpn. J. Appl. Phys.

View full text Add to dashboard Cite

EUV lithography resolves features below 11 nm. However, photonic and atomic variations at these photon energies and dimensions lead to less than 1:109 potential stochastic defects causing device failures in stable manufacturing processes. This study investigates a methodology intended to identify root causes of stochastic defects with potential mitigation paths. Simulation techniques using pseudo random numbers are used to identify failing photonic and chemical event or distribution combinations. Failing combinations occurring in many photon-chemical configurations are thought to have potential mitigation methodologies. Photonic effects demonstrated significant impacts on stochastic defect formation with approximately 73% of the photon seeds resulting in a failure in at least 60% of the trials. The material results were mixed with large failure quantities that demonstrated low impacts. The photonic shot noise based failures were dominating in this study and these failures will not be mitigated by material enhancement alone.

show abstract

“…While the industry put a lot of effort into understanding, characterizing, and mitigating the impact of stochastic effects in 0.33 NA EUV lithography [3][4][5][6][7], the focus is shifting to 0.55 NA high NA EUV which is planned for introduction beyond the sub-3nm technology node. Here, stochastic effects are expected to play an even more significant role, including their impact on device performance [8,9].…”

Section: Introductionmentioning

confidence: 99%

Electrical analysis of a stochastically simulated 2 nm node electrical test structure

Melvin¹,

Demmerle

Siebert

et al. 2023

DTCO and Computational Patterning II

View full text Add to dashboard Cite

Integrated circuit performance has been limited by transistor performance for many process nodes. However, in advanced nodes where pitches reach 10s of nanometers in size, there is an increasing probability of cases where circuit timing may be limited by the resistance and capacitance of the device rather than the transistor. This means that metal layer patterning may have implications on device performance beyond reliability, shorts, and opens. Lithography variation can be effectively predicted using stochastic simulations, including layer overlay. Simulating many patterns stochastically produces insight into the performance of the lithography process over time. Etching and metallizing the pattern set in simulation then allows the study to extend to electrical simulations. The combined lithography and electrical simulation data can then be used together to improve process or pattern performance before constructing a reticle. These data also allow the engineering teams to address resist and capacitance issues that may impact device performance prior to tapeout. This paper will investigate the metal layers of a structure designed to emulate an advanced node logic circuit that uses a CFET transistor. The structure will be corrected with OPC, and each layer will be simulated to generate a large (100) set of stochastic patterns at multiple process conditions in focus, overlay, and exposure. Each of these patterns will then be etched in a modeled process and metalized with copper. Finally, resistance and capacitance measurements will be generated from circuit simulations. The output data will then be used to update the lithography process or the pattern to improve through process performance including electrical characteristics.

show abstract

Contribution of EUV resist counting statistics to stochastic printing failures

Cited by 7 publications

References 40 publications

High-NA EUV lithography: current status and outlook for the future

High-NA EUV lithography: current status and outlook for the future

Applying stochastic simulation to study defect formation in EUV photoresists

Electrical analysis of a stochastically simulated 2 nm node electrical test structure

Contact Info

Product

Resources

About