Contour-based metrology for complex 2D shaped patterns printed by multiple-patterning process

Fuchimoto, Daisuke; Ishimoto, Toru; Shindo, Haruo; Sugahara, Hitoshi; Toyoda, Yasutaka; Mailfert, Julien; Bisschop, Peter De

doi:10.1117/12.2046783

Cited by 4 publications

(7 citation statements)

References 4 publications

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“…The attentive reader could claim we missed other potential contributors in our M1 patterning study, such as mask errors [23] , residual OPC-model errors [9] , or overlay contributions [17] . Indeed, those topics were not covered in our investigation but of course are also potential contributors indeed.…”

Section: Discussionmentioning

confidence: 97%

“… CD metrics and tolerances [16][17][18] : The case of the tip-to-line limiter structure of section 4.3 shows that a careful consideration of which metrics and tolerances should be used for determining the OPW is also essential and needs to reflect the actual requirements of the device, as a non-suitable choice may either lead to a too optimistic or too pessimistic OPW evaluation. In the example we showed, the individual PWs associated with these gaps were in fact improved by the reconsideration of the metrics/tolerances used.…”

Section: Discussionmentioning

confidence: 99%

“…Indeed, those topics were not covered in our investigation but of course are also potential contributors indeed. For example, Reference [17] reported on the same 20nm Logic node test vehicle, in which a new measurement methodology based on contour metrology was developed to quantify line-end pattern shapes and pattern placement errors. This contour-metrology method should provide useful information (pattern placement errors and line-end shapes), and could potentially be integrated in the work that was presented in this paper.…”

Section: Discussionmentioning

confidence: 99%

“…This metric cannot be directly measured by CD-SEM, as it corresponds to the distance from the printed edge to the design target. But it can be extracted from saved SEM-images using contour-based metrology [16][17] . Doing so for the case of Limiter #3, we obtained an EPE Bossung, shown in Figure 16, where we have used a threshold of +/-5nm (in agreement with the DR that was used to generate the line-end of M1, as explained in sub-section 3.2).…”

Section: Limiter #3: CD Metrics and Tolerancesmentioning

confidence: 99%

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Metal1 patterning study for random-logic applications with 193i, using calibrated OPC for litho and etch

et al. 2014

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A Metal1-layer (M1) patterning study is conducted on 20nm node (N20) for random-logic applications. We quantified the printability performance on our test vehicle for N20, corresponding to Poly/M1 pitches of 90/64nm, and with a selected minimum M1 gap size of 70nm. The Metal1 layer is patterned with 193nm immersion lithography (193i) using Negative Tone Developer (NTD) resist, and a double-patterning Litho-Etch-Litho-Etch (LELE) process. Our study is based on Logic test blocks that we OPCed with a combination of calibrated models for litho and for etch. We report the Overlapping Process Window (OPW), based on a selection of test structures measured after-etch. We find that most of the OPW limiting structures are EOL (End-of-Line) configurations. Further analysis of these individual OPW limiters will reveal that they belong to different types, such as Resist 3D (R3D) and Mask 3D (M3D) sensitive structures, limiters related to OPC (Optical Proximity Corrections) options such as assist placement, or the choice of CD metrics and tolerances for calculation of the process windows itself. To guide this investigation, we will consider a 'reference OPC' case to be compared with other solutions. In addition, rigorous simulations and OPC verifications will complete the after-etch measurements to help us to validate our experimental findings.

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Section: Discussionmentioning

confidence: 97%

Section: Discussionmentioning

confidence: 99%

Section: Discussionmentioning

confidence: 99%

Section: Limiter #3: CD Metrics and Tolerancesmentioning

confidence: 99%

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Metal1 patterning study for random-logic applications with 193i, using calibrated OPC for litho and etch

et al. 2014

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“…In multiple patterning lithographic flows, the difference between the position of the center of a resist pattern from the nominal (designed) center position, also defined as Pattern Placement Error (PPE) is considered a critical area [13][14] for process monitoring and control. As measurement of single patterning quality at the edge of features is complex, the contours were extracted using Hitachi's Design Gauge Analyzer software.…”

Section: Contour Analysismentioning

confidence: 99%

Optimum ArFi laser bandwidth for 10nm node logic imaging performance

Alagna¹,

Zurita²,

Timoshkov

et al. 2015

SPIE Proceedings

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1Cost and cycle time of multiple patterning -especially for more than 2x 2 Process control on key parameters such as overlay, CD control, LWR with multiple patterning 3 EUV Source power 4 EUV Mask Infrastructure (defect inspection and verification, mitigation, mask lifetime) Defect free EUV mask blanks, mask availability 5 EUV resist and/or process that meets sensitivity, resolution, LER requirements 1 6 DSA defecti ity and positional accuracy ABSTRACT Lithography process window (PW) and CD uniformity (CDU) requirements are being challenged with scaling across all device types. Aggressive PW and yield specifications put tight requirements on scanner performance, especially on focus budgets resulting in complicated systems for focus control. In this study, an imec N10 Logic-type test vehicle was used to investigate the E95 bandwidth impact on six different Metal 1 Logic features. The imaging metrics that track the impact of light source E95 bandwidth on performance of hot spots are: process window (PW), line width roughness (LWR), and local critical dimension uniformity (LCDU).In the first section of this study, the impact of increasing E95 bandwidth was investigated to observe the lithographic process control response of the specified logic features. In the second section, a preliminary assessment of the impact of lower E95 bandwidth was performed. The impact of lower E95 bandwidth on local intensity variability was monitored through the CDU of line end features and the LWR power spectral density (PSD) of line/space patterns. The investigation found that the imec N10 test vehicle (with OPC optimized for standard E95 bandwidth of300fm) features exposed at 200fm showed pattern specific responses, suggesting areas of potential interest for further investigation.

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Analyzing block placement errors in SADP patterning

et al. 2016

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We discuss edge placement errors (EPE) for multi-patterning of Mx critical layers using ArF lithography. Specific focus is placed on the block formation part of the process. While plenty of literature characterization data exist on spacer formation, only limited published data is available on block processes.We analyze the accuracy of placing blocks relative to narrow spacers. Many publications calculate EPE assuming Gaussian distributions for key process variations contributing to EPE. For practical reasons, each contributor is measured on dedicated test structures. In this work, we complement such analysis and directly measure the EPE in product. We perform high density sampling of blocks using CDSEM images and analyze all feature edges of interest.We find that block placement errors can be very different depending on their local design context. Specifically we report on 2 block populations (further called block A and B) which have a 4x different standard deviation. We attribute this to differences in local topography (spacer shape) and interaction with the plasma-etch process design. Block A (on top of the 'core space' S1) has excellent EPE uniformity of ~1 nm while block B (on top of 'gap space' S2) has degraded EPE control of ~4 nm.Finally, we suggest that the SOC etch process is at the origin on positioning blocks accurately on slim spacers, helping the manufacturability of spacer-based patterning techniques, and helping its extension toward the 5nm node.

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Contour-based metrology for complex 2D shaped patterns printed by multiple-patterning process

Cited by 4 publications

References 4 publications

Metal1 patterning study for random-logic applications with 193i, using calibrated OPC for litho and etch

Metal1 patterning study for random-logic applications with 193i, using calibrated OPC for litho and etch

Optimum ArFi laser bandwidth for 10nm node logic imaging performance

Analyzing block placement errors in SADP patterning

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