Context-aware resiliency: Unequal message protection for random-access memories

Schoeny, Clayton; Sala, F.; Gottscho, Mark; Alam, Irina; Gupta, Puneet; Dolecek, Lara

doi:10.1109/itw.2017.8278033

Cited by 4 publications

(3 citation statements)

References 13 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Parity++ is also evaluated with a memory speculation procedure [8] that can be generally applied to any ECC protected cache to hide the decoding latency while reading messages when there are no errors. Details of the concepts discussed in this section can be found in the work by Alam et al [1] and Schoeny et al [30].…”

Section: Parity++ : Lightweight Error Correction For Last Level Cachementioning

confidence: 99%

“…7. As in [30], there are two classes of messages, normal and special, and they are mapped to normal and special codewords, respectively. When dealing with the importance or frequency of the underlying data, it is referred to as messages; when discussing error detection/correction capabilities it is referred to as codewords.…”

Section: Parity++ Theorymentioning

confidence: 99%

“…Similar unequal message protection scheme can be used for providing DECTED protection to special messages, while non-special messages get SECDED protection. The code construction has been explained in detail in [30].…”

Section: Parity++ Theorymentioning

confidence: 99%

See 2 more Smart Citations

Lightweight Software-Defined Error Correction for Memories

Alam

Dolecek

Gupta

2020

Dependable Embedded Systems

Self Cite

View full text Add to dashboard Cite

Reliability of the memory subsystem is a growing concern in computer architecture and system design. From on-chip embedded memories in Internet-of-Things (IoT) devices and on-chip caches to off-chip main memories, the memory subsystems have become the limiting factor in the overall reliability of computing systems. This is because they are primarily designed to maximize bit storage density; this makes memories particularly sensitive to manufacturing process variation, environmental operating conditions, and aging-induced wearout. This chapter of the book focuses on software managed techniques and novel error correction codes to opportunistically cope with memory errors whenever they occur for improved reliability at minimal cost.

show abstract

Section: Parity++ : Lightweight Error Correction For Last Level Cachementioning

confidence: 99%

Section: Parity++ Theorymentioning

confidence: 99%