Contention-Aware Energy Management Scheme for NoC-Based Multicore Real-Time Systems

Han, Jian-Jun; Lin, Man; Zhu, Dakai; Yang, Laurence T.

doi:10.1109/tpds.2014.2307866

Cited by 34 publications

(35 citation statements)

References 28 publications

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“…The voltage and frequency levels are based on ORION 2.0 and the energy consumption of each router and link are extracted from 45 nm technology model of ORION which has been comparatively evaluated with a prototype chip fabricated in 45 nm SOI CMOS technology [26]. The link length between two adjacent routers is set to 1 mm and the switching activity is set to 0.5 for average switching condition, respectively [27,28]. To mitigate the implementation complexity, the maximum allowable number of VFIs is set to four.…”

Section: Resultsmentioning

confidence: 99%

Energy-efficient Custom Topology Generation for Link-failure-aware Network-on-chip in Voltage-frequency Island Regime

Li¹,

Yoo²,

Han³

2016

JSTS:Journal of Semiconductor Technology and Science

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Section: Resultsmentioning

confidence: 99%

Energy-efficient Custom Topology Generation for Link-failure-aware Network-on-chip in Voltage-frequency Island Regime

Li¹,

Yoo²,

Han³

2016

JSTS:Journal of Semiconductor Technology and Science

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“…The experiments are performed on the synthetic randomly generated precedence-constrained parallel application graphs as described below. The performance metrics chosen for the comparison are the schedule length (2) and (22), systems energy consumption EN( ) (7), and application reliability [ ] (16).…”

Section: Resultsmentioning

confidence: 99%

“…DVFS, which is a technique in which a processor runs at a less-than-maximum frequency when it is not fully utilized in order to conserve power, is perhaps the most appealing method for reducing energy consumption [14,15]. Most of the early DVFS-enabled researches focused on the single processor of embedded and real-time computing systems [14,16,17]. Recently, there has been a significant amount of work on task scheduling for heterogeneous systems using DVFS-enabled techniques.…”

Section: Related Workmentioning

confidence: 99%

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Energy-Efficient Reliability-Aware Scheduling Algorithm on Heterogeneous Systems

Tang¹,

Wei-zhen

2016

Scientific Programming

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The amount of energy needed to operate high-performance computing systems increases regularly since some years at a high pace, and the energy consumption has attracted a great deal of attention. Moreover, high energy consumption inevitably contains failures and reduces system reliability. However, there has been considerably less work of simultaneous management of system performance, reliability, and energy consumption on heterogeneous systems. In this paper, we first build the precedence-constrained parallel applications and energy consumption model. Then, we deduce the relation between reliability and processor frequencies and get their parameters approximation value by least squares curve fitting method. Thirdly, we establish a task execution reliability model and formulate this reliability and energy aware scheduling problem as a linear programming. Lastly, we propose a heuristic Reliability-Energy Aware Scheduling (REAS) algorithm to solve this problem, which can get good tradeoff among system performance, reliability, and energy consumption with lower complexity. Our extensive simulation performance evaluation study clearly demonstrates the tradeoff performance of our proposed heuristic algorithm.

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“…Multiprocessor system-on-chips (MPSoCs) are widely deployed in high-performance computing and applicationspecific embedded systems such as gaming and aerospace for real-time response. Moreover, they offer energy efficiency and performance advantages over uni-processor architectures [22]- [24]. Thus, MPSoCs are becoming the computing engines of choice in embedded systems for real-time applications.…”

Section: Implementations Of Hemelbmentioning

confidence: 99%

Heterogeneous System-on-Chip-Based Lattice-Boltzmann Visual Simulation System

Zhai

Chen

Esfahani

et al. 2020

IEEE Systems Journal

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Cerebral aneurysm is a cerebrovascular disorder caused by a weakness in the wall of an artery or vein, that causes a localised dilation or ballooning of the blood vessel. It is life-threatening, hence an early and accurate diagnosis would be a great aid to medical professionals in making the correct choice of treatment. HemeLB is a massively parallel lattice-Boltzmann simulation software which is designed to provide the radiologist with estimates of flow rates, pressures and shear stresses throughout the relevant vascular structures, intended to eventually permit greater precision in the choice of therapeutic intervention. However, in order to allow surgeries and doctors to view and visualise the results in real-time at medical environments, a cost-efficient, practical platform is needed. In this paper, we have developed and evaluated a version of HemeLB on various heterogeneous system-on-chip platforms, allowing users to run HemeLB on a low cost embedded platform and to visualise the simulation results in real-time. A comprehensive evaluation of implementation on the Zynq SoC and Jetson TX1 embedded graphic processing unit platforms are reported. The achieved results show that the proposed Jetson TX1 implementation outperforms the Zynq implementation by a factor of 19 in terms of site updates per second.

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Contention-Aware Energy Management Scheme for NoC-Based Multicore Real-Time Systems

Cited by 34 publications

References 28 publications

Energy-efficient Custom Topology Generation for Link-failure-aware Network-on-chip in Voltage-frequency Island Regime

Energy-efficient Custom Topology Generation for Link-failure-aware Network-on-chip in Voltage-frequency Island Regime

Energy-Efficient Reliability-Aware Scheduling Algorithm on Heterogeneous Systems

Heterogeneous System-on-Chip-Based Lattice-Boltzmann Visual Simulation System

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