Construction of Error Control Run Length Limited Codes Exploiting Some Parity Matrix Properties

Abstract

Error control codes (ECC) as well as translation codes (TC) are used today in many different systems such as computer storages, communications systems and consumer electronic devices. ECC introduce redundancy into the encoded digital sequence in order to decrease the number of errors at output of its decoder [1]. TC introduce redundancy, in order to translate any digital sequence at the input of TC encoder to such output sequence, which fulfills constrains deduced from practical requirements. It is possible to construct codes, which have both of these properties, so called Transcontrol codes or their subclass error control run length limited (ECRLL) codes. In this manuscript a new approach to construction of EC-RLL codes is presented. The new construction is based on some parity check matrix properties of a linear binary block code from which the new EC-RLL code is obtained.

Run length limited error control codes construction based on one control matrix property

“…1. In [16][17][18][19][20][21][22][23] the modifier formation was done using properties of G matrices described and proven in [7]. Unfortunately, the LBBC (eg LDPC codes) are often defined via their matrix and we cannot use this approach directly.…”

“…In [15] algorithms were presented for code design using finite state machines which simultaneously provide a coding gain while also mitigating flicker in VLC. In [16][17][18][19][20][21][22][23] RLLECCs were constructed using the arrangement illustrated in Fig. 1, from linear binary block codes (LBBC) using modifiers obtained based on generator matrix properties.…”

Run length limited CCSDS convolutional codes for optical communications

“…One approach to overcoming this problem with ordering the codes in cascade, at least for cascading RLL and ECCs, is to construct combined codes denoted as RLL-ECCs [11][12][13][14][15][16][17][18][19][20][21][22][23], which have RLL and error control properties simultaneously. Recently RLL-ECCs were obtained from 5G LDPC (low density parity check) codes, [11].…”

Note on Modular Reduction in Extended Finite Fields and Polynomial Rings for Simple Hardware

“…This general reduction works for any reduction polynomial, for instance [1][2][3][4][5][6], and thus we can say that it works for random reduction polynomials which can be even secret [7][8][9][10][11]. No special methods are used, and thus no processor is required, just a simple hardware can be used.…”