2010 East-West Design &Amp; Test Symposium (EWDTS) 2010
DOI: 10.1109/ewdts.2010.5742071
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Constructing test sequences for hardware designs with parallel starting operations using implicit FSM models

Abstract: The paper concerns functional testing of hardware models using finite state machines (FSM). Test construction is done by traversing FSM state graph. In this paper we propose a technique for irredundant description of FSM models of parallel-pipeline designs. The technique allows to implicitly specify complex compositional FSM models and to automate construction of test sequences by composing several parallel operations into multi-stimuli.

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