Conservation cores

Venkatesh, Ganesh; Sampson, Jack; Goulding, Nathan; Garcia, Saturnino; Bryksin, Vladyslav; Lugo-Martinez, Jose; Swanson, Steven; Taylor, Michael

doi:10.1145/1736020.1736044

Cited by 264 publications

(17 citation statements)

References 23 publications

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“…Unfortunately, there were insufficient data available to accurately compute this information. However, a substantive body of research [23][24][25][26] indicates that specialised logic consumes significantly less power than programmable logic due to the removal of overheads such as instruction processing, register accesses and inefficient memory layouts. Analyses indicate a 16× power decrease can be expected, with up to a 500× decrease possible for some applications [50].…”

Section: Resultsmentioning

confidence: 99%

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A hybrid fixed-function and microprocessor solution for high-throughput broad-phase collision detection

Woulfe

Manzke

2016

J Embedded Systems

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We present a hybrid system spanning a fixed-function microarchitecture and a general-purpose microprocessor, designed to amplify the throughput and decrease the power dissipation of collision detection relative to what can be achieved using CPUs or GPUs alone. The primary component is one of the two novel microarchitectures designed to perform the principal elements of broad-phase collision detection. Both microarchitectures consist of pipelines comprising a plurality of memories, which rearrange the input into a format that maximises parallelism and bandwidth. The two microarchitectures are combined with the remainder of the system through an original method for sharing data between a ray tracer and the collision-detection microarchitectures to minimise data structure construction costs. We effectively demonstrate our system using several benchmarks of varying object counts. These benchmarks reveal that, for over one million objects, our design achieves an acceleration of 812× relative to a CPU and an acceleration of 161× relative to a GPU. We also achieve energy efficiencies that enable the mitigation of silicon power-density challenges, while making the design amenable to both mobile and wearable computing devices.

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Section: Resultsmentioning

confidence: 99%

“…This will result in a 14 % throughput increase per annum, which is substantially less than current trends. The solution proposed by most researchers is specialisation [24][25][26], which involves offloading parallelisable computations to embedded microarchitectures. It has already been used effectively in a variety of processors.…”

Section: Microarchitecturesmentioning

confidence: 99%

A hybrid fixed-function and microprocessor solution for high-throughput broad-phase collision detection

Woulfe

Manzke

2016

J Embedded Systems

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“…Also a number of academic groups advocates this approach to accelerate many-cores. The GreenDroid architecture [21], features clusters with a single general-purpose core, which is tightly-coupled to a sea of smaller conservation cores (or c-cores) [46] that communicate with the rest of the system through a L1 coherent cache. C-cores target energy efficiency of commonly executed portions of general-purpose code, such as parts of the Android stack, by leveraging highlevel synthesis tools.…”

Section: Related Workmentioning

confidence: 99%

“…respectively silicon that is used seldom/at a lower frequency and silicon that performs specialized functions. By inserting both general and special-purpose processors in a single computing fabric we can effectively counteract the loss of potential performance due to the utilization wall, since special-purpose processors are typically not in use simultaneously nor are they always on [46]. However, heterogeneous architectures increase the size and complexity of the design space along several axes: granularity of the heterogeneous processors, coupling with software cores, communication interfaces, etc.…”

Section: Introductionmentioning

confidence: 99%

He-P2012: Performance and Energy Exploration of Architecturally Heterogeneous Many-Cores

Conti

Marongiu

Pilkington

et al. 2015

J Sign Process Syst

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The end of Dennardian scaling in advanced technologies brought about new architectural templates to overcome the so-called utilization wall and provide Moore's Law-like performance and energy scaling in embedded SoCs. One of the most promising templates, architectural heterogeneity, is hindered by high cost due to the design space explosion and the lack of effective exploration tools. Our work provides three contributions towards a scalable and effective methodology for design space exploration in embedded MC-SoCs. First, we present the He-P2012 architecture, augmenting the state-of-art STMicroelectronics P2012 platform with heterogeneous shared-L1 coprocessors called HW processing elements (HWPE). Second, we propose a novel methodology for the semi-automatic definition and instantiation of shared-memory HWPEs from a C source, supporting both simple and structured data types. Third, we demonstrate that the integration of HWPEs can provide significant performance and energy efficiency benefits on a set of benchmarks originally developed for the homogeneous P2012, achieving up to 123x speedup on the accelerated code region (∼98 % of Amdahl's law limit) while saving 2/3 of the energy.

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“…Consequently, large companies purchase computers with the best performance per energy (PPE) dollar, rather than the best absolute performance [3], and the Japanese Green IT Council promotes PPE as a world standard metric for data center efficiency [4]. To lower power and improve PPE, architects are turning to customization and heterogeneity [5], [6], [7], [8], [9], [10], [11], [12]. Customized hardware for a specific function is well known to provide orders of magnitude improvements in performance, power, or both, but offers This research was supported by ARC DP0666059, NSF CSR-0917191, the 863 program of China 2012AA010905, and the National Natural Science Foundation of China 61070037, 61103016. a daunting programming task and the resulting software is generally not portable.…”

Section: Introductionmentioning

confidence: 99%

The yin and yang of power and performance for asymmetric hardware and managed software

Cao

Blackburn

Gao

et al. 2012

SIGARCH Comput. Archit. News

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Abstract-On the hardware side, asymmetric multicore processors present software with the challenge and opportunity of optimizing in two dimensions: performance and power. Asymmetric multicore processors (AMP) combine general-purpose big (fast, high power) cores and small (slow, low power) cores to meet power constraints. Realizing their energy efficiency opportunity requires workloads with differentiated performance and power characteristics.On the software side, managed workloads written in languages such as C#, Java, JavaScript, and PHP are ubiquitous. Managed languages abstract over hardware using Virtual Machine (VM) services (garbage collection, interpretation, and/or justin-time compilation) that together impose substantial energy and performance costs, ranging from 10% to over 80%. We show that these services manifest a differentiated performance and power workload. To differing degrees, they are parallel, asynchronous, communicate infrequently, and are not on the application's critical path.We identify a synergy between AMP and VM services that we exploit to attack the 40% average energy overhead due to VM services. Using measurements and very conservative models, we show that adding small cores tailored for VM services should deliver, at least, improvements in performance of 13%, energy of 7%, and performance per energy of 22%. The yin of VM services is overhead, but it meets the yang of small cores on an AMP. The yin of AMP is exposed hardware complexity, but it meets the yang of abstraction in managed languages. VM services fulfill the AMP requirement for an asynchronous, non-critical, differentiated, parallel, and ubiquitous workload to deliver energy efficiency. Generalizing this approach beyond system software to applications will require substantially more software and hardware investment, but these results show the potential energy efficiency gains are significant.

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Conservation cores

Cited by 264 publications

References 23 publications

A hybrid fixed-function and microprocessor solution for high-throughput broad-phase collision detection

A hybrid fixed-function and microprocessor solution for high-throughput broad-phase collision detection

He-P2012: Performance and Energy Exploration of Architecturally Heterogeneous Many-Cores

The yin and yang of power and performance for asymmetric hardware and managed software

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