Connected components analysis of streamed images

Bailey, Donald G.; Johnston, C.T.; Ma, Ni

doi:10.1109/fpl.2008.4630038

Cited by 36 publications

(35 citation statements)

References 10 publications

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“…In this case, an object cannot be labeled until the end of the frame, thus producing the latency of one image frame. The claim presented in [9,27,28] is that the latency of one row is valid for only one specific case of input objects. The latency of the architecture presented in [10] is also equal to one-image frame.…”

Section: Latencymentioning

confidence: 99%

“…For the proposed architecture, there is no dependence on a row blanking period and for a frame size of 640 × 480, the maximum frame speed is around 420 frames per second. The work presented by Bailey et al [9,27,28] performs the label resolution during a horizontal blanking period. Their stack size can accommodate 128 merges.…”

Section: Quantitative Comparison With Other Architecturesmentioning

confidence: 99%

“…The latency value reported in [9,27,28] is equal to one image row. This claim of latency is only true if an image object occupies one row.…”

Section: Latencymentioning

confidence: 99%

“…Aggressive approaches were presented in [9,27,28], which only use one labeling pass and by which it is proposed that the image features can be calculated. The main emphasis of their work was to minimize the memory usage and they have, additionally, reported the worst case scenario for a number of labels.…”

Section: Related Workmentioning

confidence: 99%

“…From a typical image, many equivalent labeled pairs merge and these pairs form linked lists in the equivalence table. Resolving equivalent labels means that all the merged labels, which are linked to the same list, must be replaced by one unique label [9]. The second scan then assigns the unique label to each pixel in the image component.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Hardware Architecture for Real-Time Computation of Image Component Feature Descriptors on a FPGA

Malik

Thörnberg

Imran

et al. 2014

International Journal of Distributed Sensor Networks

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This paper describes a hardware architecture for real-time image component labeling and the computation of image component feature descriptors. These descriptors are object related properties used to describe each image component. Embedded machine vision systems demand a robust performance and power efficiency as well as minimum area utilization, depending on the deployed application. In the proposed architecture, the hardware modules for component labeling and feature calculation run in parallel. A CMOS image sensor (MT9V032), operating at a maximum clock frequency of 27 MHz, was used to capture the images. The architecture was synthesized and implemented on a Xilinx Spartan-6 FPGA. The developed architecture is capable of processing 390 video frames per second of size 640 × 480 pixels. Dynamic power consumption is 13 mW at 86 frames per second.

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Section: Latencymentioning

confidence: 99%

Section: Quantitative Comparison With Other Architecturesmentioning

confidence: 99%

“…The latency value reported in [9,27,28] is equal to one image row. This claim of latency is only true if an image object occupies one row.…”

Section: Latencymentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%