Conjugate gradient sparse solvers: performance-power characteristics

Abstract

We characterize the performance and power attributes of the conjugate gradient (CG) sparse solver which is widely used in scientific applications. We use cycle-accurate simulations with SimpleScalar and Wattch, on a processor and memory architecture similar to the configuration of a node of the BlueGene/L. We first demonstrate that substantial power savings can be obtained without performance degradation if low power modes of caches can be utilized. We next show that if Dynamic Voltage Scaling (DVS) can be used, power and energy savings are possible, but these are realized only at the expense of performance penalties. We then consider two simple memory subsystem optimizations, namely memory and level-2 cache prefetching. We demonstrate that when DVS and low power modes of caches are used with these optimizations, performance can be improved significantly with reductions in power and energy. For example, execution time is reduced by 23%, power by 55% and energy by 65% in the final configuration at 500MHz relative to the original at 1GHz. We also use our codes and the CG NAS benchmark code to demonstrate that performance and power profiles can vary significantly depending on matrix properties and the level of code tuning. These results indicate that architectural evaluations can benefit if traditional benchmarks are augmented with codes more representative of tuned scientific applications.

Analyzing Performance and Power of Multicore Architecture Using Multithreaded Iterative Solver

“…Then, using formula from (Jaleel et al, 2006, Hennessy andPatterson, 2003), the memory access time is represented as: is difficult in real computing environment. However, even with a simple memory prefetcher, the value is negligibly small in our algorithm since it accesses memory in sequential direction (Malkowski et al, 2005a;2005b).…”

Load Miss Prediction - Exploiting Power Performance Trade-offs

“…The matrix properties including the name, dimension (×10 3 ), number of nonzeros (×10 6 ) and the percentage of nonzeroes relative to a dense matrix of the same dimension are: bcsstk31, 35.6, 1.2, .09%; fdm2, 32.1,.16, .01%; qa8fm, 66.1, 1.6, .03%; and msc23052, 23.0, 1.1, .21%. These matrices had been reordered using the Reverse Cuthill McKee [17] scheme to improve the locality of access in the source vector [12] as is commonly done for tuned scientific codes.…”

“…Additionally, prefetching techniques were discussed by Lin, et al [31]. Effects of prefetchers on performance and power of sparse applications were investigated by authors in [12].…”

“…As chips approach their packaging thermal limits and cooling costs become prohibitive, power-aware design is starting to receive considerable attention in the high performance computing community [10], [11]. Sparse computations present interesting opportunities for power-aware high performance scientific computing [12] because, although they represent scalable formulations, they can achieve only a fraction of peak performance (despite extensive tuning). We conjecture that both performance and power improvements are possible by considering the co-evolution of architectural optimizations and tuned sparse matrix computations.…”

Memory Optimizations For Fast Power-Aware Sparse Computations

“…We discuss how memory optimizations that we have developed earlier [11], [15], [16] can affect the performance of tuned and un-tuned versions of sparse matrix vector multiplication. We consider the use of such optimizations with powersaving modes of the hardware such as Dynamic Voltage and Frequency Scaling (DVFS) [5] to improve performance at significantly lower power levels.…”