Congestion-aware Network-on-Chip router architecture

Wang, Chifeng; Hu, Wen-Hsiang; Bagherzadeh, Nader

doi:10.1109/cads.2010.5623552

Cited by 25 publications

(14 citation statements)

References 15 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Although the Clos-UDN [8] [9], has good scalability and flexibility features, the switch, as other proposals, deals blindly with congestion. Dimension Order Routing (DOR) methods that a Clos-UDN switch uses, are simple to implement in hardware [21]. Conversely, they poorly disperse the traffic load among links of the NoC.…”

Section: Limitation Of Previous Workmentioning

confidence: 99%

Congestion-Aware Multistage Packet-Switch Architecture for Data Center Networks

Hassen

Mhamdi

2016

2016 IEEE Global Communications Conference (GLOBECOM)

View full text Add to dashboard Cite

Abstract-Data Center Networks (DCNs) have gone through major evolutionary changes over the past decades. Yet, it is still difficult to predict loads fluctuation and congestion spikes in the network switching fabric. Conventional multistage switches/routers used in data center fabrics barely deal with load balancing. Congestion management is often processed at the edge modules. However, neither the architecture of switches/routers, nor their inner routing algorithms tend to consider traffic balancing and congestion management. In this paper, we propose a flexible design of a scalable multistage switch with crossconnected UniDirectional Network-on-Chip based central blocs (UDNs). We also introduce a congestion-aware routing to forward packets adaptively. We compare the current switch architecture to the state-of-the art previous multistage switches under different traffic types. Simulations of various switch settings have shown that the proposed architecture maintains high throughput and low latency performance.

show abstract

Section: Limitation Of Previous Workmentioning

confidence: 99%

Congestion-Aware Multistage Packet-Switch Architecture for Data Center Networks

Hassen

Mhamdi

2016

2016 IEEE Global Communications Conference (GLOBECOM)

View full text Add to dashboard Cite

show abstract

“…A proposed lightweight dynamic arbitration mechanism has shown that its effectiveness in congestion detection and management [46,47]. The mechanism can especially reduce the wiring requirement because it only delivers congestion index calculated by the number of active FIFOs with waiting packets instead of detailed buffer or link information.…”

Section: Dynamic Congestion-aware Router Architecturementioning

confidence: 99%

“…In order to design a lightweight congestion-aware NoC router, an approach based on dynamic port arbitration to resolve congestion and adaptive output path selection to distribute traffic load efficiently was devised [45,46]. Complicated buffer monitor methods will cause more overhead for multi-port designs such as NePA and DMesh routers.…”

Section: Congestion Controlmentioning

confidence: 99%

Design and evaluation of a high throughput QoS-aware and congestion-aware router architecture for Network-on-Chip

Wang

Bagherzadeh

2014

Microprocessors and Microsystems

Self Cite

View full text Add to dashboard Cite

a b s t r a c tThis paper proposes a novel QoS-aware and congestion-aware Network-on-Chip architecture that not only enables quality-oriented network transmission and maintains a feasible implementation cost but also well balance traffic load inside the network to enhance overall throughput. By differentiating application traffic into different service classes, bandwidth allocation is managed accordingly to fulfill QoS requirements. Incorporating with congestion control scheme which consists of dynamic arbitration and adaptive routing path selection, high priority traffic is directed to less congested areas and is given preference to available resources. Simulation results show that average latency of high priority and overall traffic is improved dramatically for various traffic patterns. Cost evaluation results also show that the proposed router architecture requires negligible cost overhead but provides better performance for both advanced mesh NoC platforms.

show abstract

“…In NoC architecture design, many efforts are focused on increasing the total bandwidth and reducing the average node distance by proposing new topologies [118,119]. In [118], a Diagonally-linked Mesh topology is proposed which employs physical diagonal express links between routers to reduce the distances between nodes.…”

Section: Introductionmentioning

confidence: 99%

“…In [118], a Diagonally-linked Mesh topology is proposed which employs physical diagonal express links between routers to reduce the distances between nodes. In [119], a new topology called Multidrop Express Channels (MECS) is proposed; this uses a one-to-many communication model to enable a high degree of connectivity.…”

Section: Introductionmentioning

confidence: 99%

High performance network-on-chips (NoCs) design : performance modeling, routing algorithm and architecture optimization

Qian¹

View full text Add to dashboard Cite

TABLE OF CONTENTS Title Page i Authorization Page ii Signature Page iiiAcknowledgments iv Table of Contents v List of Figures ix List of Tables xiiiAbstract xiv Therefore, fast and accurate analytical models for NoC-based multicore performance evaluation are strongly desired to better explore the design space. For this purpose, we propose a machine learning based latency regression model to evaluate the NoC designs with respect to different configurations before the system is built or taped-out. Then, for high performance NoC designs, we tackle one of the most important problems, i.e., the routing algorithms design with different design constraints and objectives. For avoiding temperature hotspots, a thermal-aware routing algorithm is proposed to achieve an even temperature profile for application-specific Network-on-chips (NoCs). For improving the reliability, a routing algorithm to achieve maximum performance under fault is proposed. Finally, in the architecture level, we propose two new NoC structures using bi-directional links for the performance optimization. In particular, we propose a flit-level speedup scheme to enhance the network-on-chip(NoC) performance utilizing bidirectional channels. In addition to the traditional efforts on allowing flits of different packets using the idling internal and external bandwidth of the bidirectional channel, our proposed flit-level speedup scheme also allows flits within the same packet to be transmitted simultaneously on the bi-directional channel.We also propose a flexible NoC architecture which takes advantage of a dynamic distributed routing algorithm and improves the NoC communication performance with minimal energy overhead. This proposed NoC architecture exploits the selfreconfigurable bidirectional channels to increase the effective bandwidth and uses express virtual paths, as well as localized hub routers, to bypass some intermediate nodes at run time in the network. From the simulation results on both synthetic traffic and real workload traces, significantly performance improvement in terms of latency and throughput can be achieved.

show abstract

Congestion-aware Network-on-Chip router architecture

Cited by 25 publications

References 15 publications

Congestion-Aware Multistage Packet-Switch Architecture for Data Center Networks

Congestion-Aware Multistage Packet-Switch Architecture for Data Center Networks

Design and evaluation of a high throughput QoS-aware and congestion-aware router architecture for Network-on-Chip

High performance network-on-chips (NoCs) design : performance modeling, routing algorithm and architecture optimization

Contact Info

Product

Resources

About