Conformal deposition of electroless barrier and seed layers in TSV with Au nano particle catalyst

Inoue, Fumihiro; Yokoyama, Takumi; Miyake, Hidekazu; Tanaka, Shukichi; Yamamoto, Kousaku; Shingubara, Shoso

doi:10.1109/iitc.2010.5510734

Cited by 4 publications

(6 citation statements)

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“…Further, annealing studies on the copper TSV have been conducted, and results reported in [42]. Other researchers have focused on Ni alloys as the material of choice [38,40]. Joseph et al [25] report on the use of tungstenfilled, multifinger, bar-shaped TSVs in an interposer designed to deliver a low-inductance ground to the package.…”

Section: Tsv Processesmentioning

confidence: 97%

“…polymers, followed by appropriate thermal processing and removal of excess material from the surface. Extensive work has been done in the development of each of these processes, and the characterization of the resulting TSV's at a variety of dimensions and pitches [24][25][26][27][28][29][30][31][32][33][34][35][36][37][38][39][40][41][42][43].…”

Section: Tsv Processesmentioning

confidence: 99%

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3D integration review

Farooq¹,

Iyer²

2011

Sci. China Inf. Sci.

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3-D integration delivers value by increasing the volumetric transistor density with the potential benefit of shorter electrical path lengths through use of the shorter third dimension. Several researchers have studied various aspect of 3Di such as bonding level, through silicon via processes and integration, thermomechanical reliability of the vias, and the impact of the vias on devices. In this paper, we review some of the literature with a view to understanding the key options and challenges in 3Di. We also discuss some important applications of this technology, and the constraints that have to be overcome to make it work.

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Section: Tsv Processesmentioning

confidence: 97%

Section: Tsv Processesmentioning

confidence: 99%

3D integration review

Farooq¹,

Iyer²

2011

Sci. China Inf. Sci.

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“…Plating have advantages among others on low cost, thin layer control, good throwing power on dead corner coverage. Meanwhile the drawbacks plating is the environmentally challenge and backside coating is needed to cover the not-to-plated area [6]. Figure 1 illustrates the conventional versus new approach on EMI shielding by plating.…”

Section: 0 Emi Shielding Fabrication Techniquementioning

confidence: 99%

EMI Shielding by Plating Technique and Its Performance on the Shielding Effectiveness

2019

IJRTE

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In the effort to miniaturize the electronic packaging, plating on mold compound has been in intensively studied as a solution to replace the metal can for Electro-Magnetic Interference (EMI) shielding. Plating technique is capable to reduce 5 to 10 times space compare to the metal can. A pre-shielded package can be done by plating in an array form before send to the die cut. This will enable shielding in bulk hence reduce the manufacturing foot print and cost. In our past research work, we had demonstrated a feasible manufacturing process, and the plated product had reached the high reliable performance [1]. Following the research, we design a series of microstrip patch antennas to evaluate the effectiveness of EMI shielding by the plating technique, in frequency of 2.65, 6.26 and 10.0GHz. Antennas are coated with conformal coat ink as the insulator, followed by plating of the nickel-phosphorous (NiP) and the pure copper (Cu). The capability of plated metal shield to attenuate the antenna receiving power, is used to evaluate the performance of EMI shielding effectiveness (SE). Result showed a direct co-relation of the metal thickness towards EMI shielding effectiveness, but it come into saturation when we further increase the thicknesses. Besides, test also shown material selection on copper versus nickel-phosphorous with its high differences on conductivity and permeability properties, resulting in different EMI shielding performance at different frequency. The combination of 2 different metals enhance the EMI shielding result compare to single metal

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“…The TSV process comprises via etching, via insulation, deposition of the diffusion barrier/liner/seed, deposition of the metal/alloy to fill the TSV, followed by appropriate thermal processing and removal of any overburden. Extensive work has been done in the fabrication, integration, and characterization of TSVs (27,(29)(30)(31)(32)(33)(34)(35)(36)(37)(38)(39)(40)(41)(42)(43)(44)(45)(46)(47). The TSVs may be etched first before any other process, or last, from the backside of thinned wafer, as shown in Figure 7 compared very deep TSVs, in the 100 μm range, with AR approaching 50:1 in the FEOL (29).…”

Section: Tsv Processesmentioning

confidence: 99%

“…Silicon etching may be achieved with the Bosch process, using alternating cycles of passivation (C 4 F 8 ) to prevent lateral etching, followed by silicon etch (SF 6 ) which gives an AR (Aspect Ratio) of > 40:1 (47,48). Several researchers have used the Bosch method (40,42,43,49,57). Others have investigated non-Bosch processes, such as a magnetically-enhanced capacitively-coupled plasma etch method, to achieve an AR approaching 30:1 (45) or an enhanced etch process to achieve deep vias with minimal sidewall scalloping (36).…”

Section: Tsv Processesmentioning

confidence: 99%

(Invited) 3D Integration in Silicon Technology

Farooq¹

2011

ECS Trans.

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3Di (3D integration) refers to a family of technologies which enable the stacking of active Si layers with vertical connections between them. 3Di has the ability to enhance chip performance by increasing bandwidth, reducing wire delay, and enabling better power management. Several researchers have investigated TSV (Through Silicon Via) fabrication, insulation, metallization, integration, the impact of TSVs on devices, thermo-mechanical integrity and reliability of TSVs. This paper presents a review of some of these publications in order to understand the options and challenges in 3Di.

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Conformal deposition of electroless barrier and seed layers in TSV with Au nano particle catalyst

Cited by 4 publications

References 5 publications

3D integration review

3D integration review

EMI Shielding by Plating Technique and Its Performance on the Shielding Effectiveness

(Invited) 3D Integration in Silicon Technology

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