Confined PCM-based Analog Synaptic Devices offering Low Resistance-drift and 1000 Programmable States for Deep Learning

Kim, W.; Bruce, Robert L.; Masuda, Takeshi; Fraczak, Gloria; Gong, N.; Adusumilli, Praneet; Ambrogio, Stefano; Tsai, Hsinyu; Bruley, J.; Han, Jin‐Ping; Longstreet, M.; Carta, Fabio; Suu, Koukou; BrightSky, M.

doi:10.23919/vlsit.2019.8776551

Cited by 54 publications

(30 citation statements)

References 2 publications

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“…Even though the multilevel resistance has already been achieved, another nontrivial challenge known as the resistance drift, i.e., the spontaneous change in resistance over time, would cause the data error in such delicate PCM devices. To address this issue, Kim et al [144] utilized the confined PCM devices as synaptic elements to suppress the resistance drift. The low drift coefficient is achieved (υ = 0.005) with high endurance (>2 × 10 11 cycles).…”

Section: (11 Of 21)mentioning

confidence: 99%

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Recent Advances on Neuromorphic Devices Based on Chalcogenide Phase‐Change Materials

Mai

Lin

et al. 2020

Adv Funct Materials

172

120

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Traditional von Neumann computing architecture with separated computation and storage units has already impeded the data processing performance and energy efficiency, calling for emerging neuromorphic electronic and optical devices and systems which can mimic the human brain to shift this paradigm. Material-level innovation has become the key component to this revolution of information technology. Chalcogenide phase-change material (PCM) as a well-acknowledged data-storage medium is a promising candidate to tackle this challenge. In this review, the use of PCMs to implement artificial neurons and synapses from both the electronic and optical respects is discussed, and in particular, the structure-property physics and transition dynamics that enable such brain-inspired and in-memory computing applications are emphasized. Recent advances on the atomic-level amorphous and crystalline structures, transition mechanisms, materials optimization and design, neural and synaptic devices, brain-inspired chips, and computing systems, as well as the future opportunities of PCMs, are summarized and discussed.

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Section: (11 Of 21)mentioning

confidence: 99%

“…To address this issue, Kim et al. [ 144 ] utilized the confined PCM devices as synaptic elements to suppress the resistance drift. The low drift coefficient is achieved (υ = 0.005) with high endurance (>2 × 10 11 cycles).…”

Section: Electronic Brain‐inspired Devices With Pcmsmentioning

confidence: 99%

Recent Advances on Neuromorphic Devices Based on Chalcogenide Phase‐Change Materials

Mai

Lin

et al. 2020

Adv Funct Materials

172

120

View full text Add to dashboard Cite

show abstract

“…Emerging eNVM devices such as RRAM [2], PCM [3], EpiRAM [4], ECRAM [5] and FeFET [6] have been proposed by the device community as candidates of "analog" synaptic devices, to represent the weights of deep CNNs in CIM accelerators. To evaluate these device properties from systemlevel perspective, we published a prior work in IEDM 2019 [7], whose latest version is named as DNN+NeuroSim V1.1, and served as an end-to-end benchmarking framework for the inference engine design.…”

Section: Introductionmentioning

confidence: 99%

DNN+NeuroSim: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators with Versatile Device Technologies

Peng

Huang

Luo

et al. 2019

2019 IEEE International Electron Devices Meeting (IEDM)

220

105

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DNN+NeuroSim is an integrated framework to benchmark compute-in-memory (CIM) accelerators for deep neural networks, with hierarchical design options from devicelevel, to circuit-level and up to algorithm-level. A python wrapper is developed to interface NeuroSim with a popular machine learning platform: Pytorch, to support flexible network structures. The framework provides automatic algorithm-to-hardware mapping, and evaluates chip-level area, energy efficiency and throughput for training or inference, as well as training/inference accuracy with hardware constraints. Our prior work (open-source framework DNN+NeuroSim V1.1: https://github.com/neurosim/DNN_NeuroSim_V1.1) was developed to estimate the impact of reliability in synaptic devices, and analog-to-digital converter (ADC) quantization loss on the accuracy and hardware performance of inference engines. In this work, we further investigated the impact of the "analog" emerging non-volatile memory (eNVM)'s non-ideal device properties for on-chip training. By introducing the nonlinearity, asymmetry, device-to-device and cycle-to-cycle variation of weight update into the python wrapper, and peripheral circuits for error/weight gradient computation in NeuroSim core, we benchmarked CIM accelerators based on state-of-the-art SRAM and eNVM devices for VGG-8 on CIFAR-10 dataset, revealing the crucial specs of synaptic devices for on-chip training. The proposed DNN+NeuroSim V2.0 framework is available on GitHub at https://github.com/neurosim/DNN_NeuroSim_V2.0.

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“…CIM accelerators based on the mainstream device technologies such as SRAM [3][4], NOR Flash [5] and NAND Flash [6][7][8][9] have been proposed and verified in silicon. Furthermore, the emerging nonvolatile (NVM) memories such as RRAM [10][11][12][13][14][15] and PCM [16][17] have been considered as strong candidates due to the multilevel capability (over SRAM) and lower programming voltage (over Flash).…”

Section: Introductionmentioning

confidence: 99%

Ferroelectric Field-Effect Transistor-Based 3-D NAND Architecture for Energy-Efficient on-Chip Training Accelerator

Shim

2021

IEEE J. Explor. Solid-State Comput. Devices Circuits

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Different from the deep neural network (DNN) inference process, the training process produces huge amount of intermediate data to compute the new weights of the network. Generally, on-chip global buffer (e.g. SRAM cache) has limited capacity because of its low memory density, therefore the off-chip DRAM access is inevitable during the training sequences. In this work, a novel ferroelectric field effect transistor (FeFET) based 3D NAND architecture for on-chip training accelerator is proposed. The reduced peripheral circuit overheads owing to the low operation voltage of FeFET device and ultra-high density of 3D NAND architecture enables storing and computing all the intermediate data on chip during the training process. We present a custom design of 108 Gb chip with 59.91 mm 2 area with 45 % array efficiency. The relevant data mapping schemes for weights/activations/errors that are compatible to the 3D NAND architecture are investigated. The training performance was explored while ResNet-18 model is trained on this architecture with ImageNet dataset by 8-bit precision. Thanks to the minimized off-chip memory access, 7.76 TOPS/W of energy efficiency was achieved for 8-bit on-chip training.

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Confined PCM-based Analog Synaptic Devices offering Low Resistance-drift and 1000 Programmable States for Deep Learning

Cited by 54 publications

References 2 publications

Recent Advances on Neuromorphic Devices Based on Chalcogenide Phase‐Change Materials

Recent Advances on Neuromorphic Devices Based on Chalcogenide Phase‐Change Materials

DNN+NeuroSim: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators with Versatile Device Technologies

Ferroelectric Field-Effect Transistor-Based 3-D NAND Architecture for Energy-Efficient on-Chip Training Accelerator

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