Configurations of memristor-based APUF for improved performance

Abstract

The memristor-based arbiter PUF (APUF) has great potential to be used for hardware security purposes. Its advantage is in its challenge-dependent delays, which cannot be modeled by machine learning algorithms. In this paper, further improvement is proposed, which are circuit configurations to the memristor-based APUF. Two configuration aspects were introduced namely varying the number of memristor per transistor, and the number of challenge and response bits. The purpose of the configurations is to introduce additional variation to the PUF, thereby improve PUF performance in terms of uniqueness, uniformity, and bit-aliasing; as well as resistance against support vector machine (SVM). Monte Carlo simulations were carried out on 180 nm and 130 nm, where both CMOS technologies have produced uniqueness, uniformity, and bit-aliasing values close to the ideal 50%; as well as SVM prediction accuracies no higher than 52.3%, therefore indicating excellent PUF performance.

Memristive Physical Unclonable Functions: The State-of-the-Art Technology

“…The authors [74] validated a PUF circuit by experiment. In the study [75], to authenticate users and perform sneak path integrity checks on stored data in the crossbar array, the authors included a PUF circuit. They showed how memristive crossbar arrays might be used for both memory and PUF applications.…”

Application of Memristors in Hardware Security: A Current State‐of‐the‐Art Technology

“…b) Modified memristor‐based PUF circuit; Reproduced with permission. [ 94 ] Copyright 2019, Institute of Advanced Engineering and Science. Panel 2. a) ROPUF based on CMOS; Reproduced with permission.…”

“…Copyright 2015, the Royal Society of Chemistry. b) Modified memristor-based PUF circuit; Reproduced with permission [94]. Copyright 2019, Institute of Advanced Engineering and Science.…”