Conduction and material transport phenomena of degradation in electrically stressed ultra low-k dielectric before breakdown

Breuer, Thomas; Kerst, U.; Boit, Christian; Langer, Eckhard; Ruelke, H.; Fissel, A.

doi:10.1063/1.4768918

Cited by 13 publications

(9 citation statements)

References 15 publications

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“…247 Integrated requirements.-Cu/metal diffusion resistance.-An obvious integrated requirement for any dielectric diffusion barrier / metal capping layer is to prevent diffusion of the metal wire into the surrounding ILD. The presence of metal contamination in the ILD has been attributed to a number of reliability issues 248 such as increased leakage currents, [249][250][251] decreased TDDB lifetime [252][253][254][255][256][257][258] and shifts in CMOS device performance. [259][260][261][262][263][264] A number of Cu barrier performance tests have been reported in the literature.…”

Section: -122mentioning

confidence: 99%

Dielectric Barrier, Etch Stop, and Metal Capping Materials for State of the Art and beyond Metal Interconnects

King

2014

ECS J. Solid State Sci. Technol.

131

115

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Over the past decade, the primary focus for improving the performance of nano-electronic metal interconnect structures has been to reduce the impact of resistance-capacitance (RC) delays via utilizing insulating dielectrics with ever lower values of dielectric permittivity. The integration and implementation of such low dielectric constant (i.e. low-k) materials has been fraught with numerous challenges. For intermetal and interlayer (ILD) low-k dielectrics, these challenges have been largely associated to integration with metal interconnect fabrication processes and well documented and reviewed in the literature. Although equally important, less attention has been given to other low-k dielectrics utilized in metal interconnect structures that are commonly referred to as low-k dielectric barriers (DB), etch stops (ES), and/or Cu capping layers (CCL). These materials present numerous challenges as well for integration into metal interconnect fabrication processes. However, they also have more stringent integrated functionality requirements relative to low-k ILD materials that serve only a basic purpose of electrically isolating adjacent metal lines. In this article, we review the integration challenges and associated integrated functionality requirements for low-k DB/ES/CCL materials with a focus on the current status and future direction needed for these materials to facilitate both Moore's law (i.e. More Moore) and More than Moore scaling.

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Section: -122mentioning

confidence: 99%

Dielectric Barrier, Etch Stop, and Metal Capping Materials for State of the Art and beyond Metal Interconnects

King

2014

ECS J. Solid State Sci. Technol.

131

115

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“…Dedicated experiments have been performed to investigate the TDDB failure mechanism [7][8][9] , and a significant amount of effort has been invested to develop models which describe the relationship between electric field and lifetime of the devices [10][11][12][13] . The existing studies benefit the community of reliability engineers in microelectronics; however, many challenges still exist and many questions still need to be answered in detail.…”

Section: Introductionmentioning

confidence: 99%

<em>In Situ</em> Time-dependent Dielectric Breakdown in the Transmission Electron Microscope: A Possibility to Understand the Failure Mechanism in Microelectronic Devices

Liao

Gall

Yeap

et al. 2015

JoVE

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The time-dependent dielectric breakdown (TDDB) in on-chip interconnect stacks is one of the most critical failure mechanisms for microelectronic devices. The aggressive scaling of feature sizes, both on devices and interconnects, leads to serious challenges to ensure the required product reliability. Standard reliability tests and post-mortem failure analysis provide only limited information about the physics of failure mechanisms and degradation kinetics. Therefore it is necessary to develop new experimental approaches and procedures to study the TDDB failure mechanisms and degradation kinetics in particular. In this paper, an in situ experimental methodology in the transmission electron microscope (TEM) is demonstrated to investigate the TDDB degradation and failure mechanisms in Cu/ULK interconnect stacks. High quality imaging and chemical analysis are used to study the kinetic process. The in situ electrical test is integrated into the TEM to provide an elevated electrical field to the dielectrics. Electron tomography is utilized to characterize the directed Cu diffusion in the insulating dielectrics. This experimental procedure opens a possibility to study the failure mechanism in interconnect stacks of microelectronic products, and it could also be extended to other structures in active devices. Video LinkThe video component of this article can be found at

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“…Interconnects in particular have unique nanoscale electrical, thermal, and mechanical challenges. [72][73][74] Unlike CMOS Dennard device scaling in previous decades, 18 interconnect electrical performance actually degrades with dimensional scaling and can impose significant limitations on integrated circuit performance through critical path signal delay.…”

mentioning

confidence: 99%

Research Updates: The three M's (materials, metrology, and modeling) together pave the path to future nanoelectronic technologies

et al. 2013

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Recent discussions concerning the continuation of Moore's law have focused on announcements by several major corporations to transition from traditional 2D planar to new 3D multi-gate field effect transistor devices. However, the growth and progression of the semiconductor microelectronics industry over the previous 4 decades has been largely driven by combined advances in new materials, lithography, and materials related process technologies. Looking forward, it is therefore anticipated that new materials and materials technologies will continue to play a significant role in both the pursuit of Moore's law and the evolution of the industry. In this research update, we discuss and illustrate some of the required and anticipated materials innovations that could potentially lead to the continuation of Moore's law for another decade (or more). We focus primarily on the innovations needed to achieve single digit nanometer technologies and illustrate how at these dimensions not only new materials but new metrologies and computational modeling will be needed.

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Conduction and material transport phenomena of degradation in electrically stressed ultra low-k dielectric before breakdown

Cited by 13 publications

References 15 publications

Dielectric Barrier, Etch Stop, and Metal Capping Materials for State of the Art and beyond Metal Interconnects

Dielectric Barrier, Etch Stop, and Metal Capping Materials for State of the Art and beyond Metal Interconnects

<em>In Situ</em> Time-dependent Dielectric Breakdown in the Transmission Electron Microscope: A Possibility to Understand the Failure Mechanism in Microelectronic Devices

Research Updates: The three M's (materials, metrology, and modeling) together pave the path to future nanoelectronic technologies

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