2020 IEEE 31st International Conference on Application-Specific Systems, Architectures and Processors (ASAP) 2020
DOI: 10.1109/asap49362.2020.00013
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Condensing an overload of parallel computing ingredients into a single architecture recipe

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Cited by 4 publications
(6 citation statements)
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“…The BM is at the 3rd level in the memory hierarchy of the DRAGON architecture, the first being the Register File, the second being the LM and the last being the GM. In [3]- [5], the BM was implemented as a single dual-ported block that is composed of 16 Ultra RAMs. The inputs and outputs of the first port were shared by all PEs.…”
Section: B the Dragon Accelerator 1) The Broadcast Cluster The Broadcast Memory And The Broadcast Memory Controllermentioning
confidence: 99%
See 4 more Smart Citations
“…The BM is at the 3rd level in the memory hierarchy of the DRAGON architecture, the first being the Register File, the second being the LM and the last being the GM. In [3]- [5], the BM was implemented as a single dual-ported block that is composed of 16 Ultra RAMs. The inputs and outputs of the first port were shared by all PEs.…”
Section: B the Dragon Accelerator 1) The Broadcast Cluster The Broadcast Memory And The Broadcast Memory Controllermentioning
confidence: 99%
“…This datum can come from any BM bank, thus all these banks are accessible to all PEs and the original BM size in previous implementation can be emulated by combining storage capacity of all 16 BM banks. Moreover, in [3]- [5], since the BM data input was shared by all the 16 PEs in the cluster, storing data to BM was done in a sequential manner. A sampler was used to register the PE data outputs and to serialize them to the BM input port.…”
Section: B the Dragon Accelerator 1) The Broadcast Cluster The Broadcast Memory And The Broadcast Memory Controllermentioning
confidence: 99%
See 3 more Smart Citations