Concurrent min-max simulation

Ulrich, Ernst G.; Lentz, K.P.; Demba, S.; Razdan, R.

doi:10.1109/edac.1991.206469

Cited by 10 publications

(7 citation statements)

References 3 publications

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“…Increasing process variation in sub-micron devices has prompted research in various directions, including Monte-Carlo techniques [14,18,27], bounded delay simulation [4,11,12,17,25], statistical timing analysis [2,3,26,28] and the classical bounded delay timing analysis [7]. Timing analysis finds corners in the design process in a vector independent manner by using specified gate delays.…”

Section: Introductionmentioning

confidence: 99%

Delay Test Quality Evaluation Using Bounded Gate Delays

Bose

Agrawal

2007

25th IEEE VLSI Test Symposium (VTS'07)

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Conventionally, path delay tests are derived in a delay-independent manner, which causes most faults to be robustly untestable. Many non-robust tests are invalidated by hazards caused primarily due to non-zero delays of off-path circuit elements. Thus, non-robust tests are of limited value when process variations change gate delays. We propose a bounded gate delay model for test quality evaluation and give a novel simulation algorithm that is less pessimistic than previous approaches. The key idea is that certain time-correlations among the multiple transitions at the inputs of a gate cannot cause hazard at its output. We maintain "ambiguity lists" for gates. These are propagated with events, similar to fault lists in a traditional concurrent fault simulation. They are used to suppress erroneous unknown states. Experimental results for ISCAS benchmarks with gate delay variation of ±14% show a miscorrelation of critical path delay as much as 20%.

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Section: Introductionmentioning

confidence: 99%

Delay Test Quality Evaluation Using Bounded Gate Delays

Bose

Agrawal

2007

25th IEEE VLSI Test Symposium (VTS'07)

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“…Our simulator produces timing results more accurate than those obtainable with previous polynomial-time min-max timing simulation algorithms [3,22], particularly in the presence of nested reconvergent fanouts. Our polynomial-time reconvergerit fanout analysis is also able to detect some event-orderlings not detectable with a previously published exponential-time simulator [ 191.…”

Section: Introductionmentioning

confidence: 72%

“…Note that G9.del[Al] = [4,9] and G7.del[Al] = [2,7], so the transitions on G7 and G9 would appear to overlap if we used only the del arrays, as in [3]. If we were to analyze these circuits using the reconvergent fanout analysis proposed in [22], then we would find that in subcircuit Kanehara-0, a glitch is produced at Y 1 by P-machines originating from A1 ad A2, and also by an S-machine originating from G1. The analysis in [22] would therefore indicate the presence of a glitch on Y 1.…”

Section: Ifmentioning

confidence: 98%

“…If we were to analyze these circuits using the reconvergent fanout analysis proposed in [22], then we would find that in subcircuit Kanehara-0, a glitch is produced at Y 1 by P-machines originating from A1 ad A2, and also by an S-machine originating from G1. The analysis in [22] would therefore indicate the presence of a glitch on Y 1. Similarly, their analysis would indicate the possibility of a glitch on Y2.…”

Section: Ifmentioning

confidence: 99%

“…These bounds can then be used to determine constraints for proper circuit operation, e.g., minimum delay between successive input transitions in fundamental-mode circuits. Previously, Ulrich, Lentz, Demba and Razdan [22] have reported a polynomial-time min-max timing simulator of this type. However, their results are extremely pessimistic in the presence of nested reconvergent fanouts.…”

Section: Introductionmentioning

confidence: 98%

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More accurate polynomial-time min-max timing simulation

Chakraborty

Dill

Proceedings Third International Symposium on Advanced Research in Asynchronous Circuits and Systems

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We describe a polynomial-time algorithm for min-max timing simulation of combinational circuits. Our algorithm reports conservative bounds on the propagation delays from each primary input to each gate, for use in the timing veri-$cation of fundamental-mode asynchronous circuits. A new reconvergent fanout analysis technique is presented. Our algorithm produces more accurate results than previous polynomial-time (and some exponential-time) algorithms in the presence of reconvergent fanouts.

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Concurrent and Comparative Discrete Event Simulation

Ulrich

Agrawal

Arabian

1994

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Concurrent min-max simulation

Cited by 10 publications

References 3 publications

Delay Test Quality Evaluation Using Bounded Gate Delays

Delay Test Quality Evaluation Using Bounded Gate Delays

More accurate polynomial-time min-max timing simulation

Concurrent and Comparative Discrete Event Simulation

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