Concurrent error detection of fault-based side-channel cryptanalysis of 128-bit RC6 block cipher

Wu, Kaijie; Mishra, Piyush; Karri, Ramesh

doi:10.1016/s0026-2692(02)00126-x

Cited by 5 publications

(4 citation statements)

References 10 publications

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“…In general, most fault-tolerant design techniques, such as temporal and spatial redundancy, can be applied to mitigate certain types of faults. These techniques include Concurrent Error Detection (CED) [121][122][123][124][125][126][127][128][129][130], error detection/correction code [131][132][133][134][135][136][137][138][139][140][141][142][143], modular redundancy [144,145], Built-In Self-Test (BIST) [146], and algorithm modification [147][148][149][150][151][152][153]. In addition, the use of dual-rail encoding and its fault analysis can be found in [130,[154][155][156].…”

Section: Fault-based Attacksmentioning

confidence: 99%

Delay Insensitive Ternary CMOS Logic for Secure Hardware

Nair

Smith

2015

JLPEA

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As digital circuit design continues to evolve due to progress of semiconductor processes well into the sub 100 nm range, clocked architectures face limitations in a number of cases where clockless asynchronous architectures generate less noise and produce less electromagnetic interference (EMI). This paper develops the Delay-Insensitive Ternary Logic (DITL) asynchronous design paradigm that combines design aspects of similar dual-rail asynchronous paradigms and Boolean logic to create a single wire per bit, three voltage signaling and logic scheme. DITL is compared with other delay insensitive paradigms, such as Pre-Charge Half-Buffers (PCHB) and NULL Convention Logic (NCL) on which it is based. An application of DITL is discussed in designing secure digital circuits resistant to side channel attacks based on measurement of timing, power, and EMI signatures. A Secure DITL Adder circuit is designed at the transistor level, and several variance parameters are measured to validate the efficiency of DITL in resisting side channel attacks. The DITL design methodology is then applied to design a secure 8051 ALU.

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Section: Fault-based Attacksmentioning

confidence: 99%

Delay Insensitive Ternary CMOS Logic for Secure Hardware

Nair

Smith

2015

JLPEA

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“…On the other hand, several countermeasures that detect errors in processing have also been proposed [14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29]. Fig.…”

Section: Introductionmentioning

confidence: 99%

“…1(b), two encryption operations for the same data in the register RegX are performed by duplicated round function blocks, and the results are compared [24]. The architecture of Fig.…”

Section: Introductionmentioning

confidence: 99%

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High-Performance Concurrent Error Detection Scheme for AES Hardware

Satoh

Sugawara

Homma

et al.

Cryptographic Hardware and Embedded Systems – CHES 2008

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Abstract. This paper proposes an efficient concurrent error detection scheme for hardware implementation of the block cipher AES. The proposed scheme does not require an additional arithmetic unit, but simply divides the round function block into two sub-blocks and uses the subblocks alternately for encryption (or decryption) and error detection. The number of clock cycles is doubled, but the maximum operating frequency is increased owing to the shortened critical path of the sub-block. Therefore, the proposed scheme has a limited impact on hardware performance with respect to size and speed. AES hardware with the proposed scheme was designed and synthesized using a 90-nm CMOS standard cell library with size and speed optimization options. The compact and high-speed implementations achieved performances of 2.21 Gbps @ 16.1 Kgates and 3.21 Gbps @ 24.1 Kgates, respectively. In contrast, the performances of AES hardware without error detection were 1.66 Gbps @ 12.9 Kgates for the compact version and 4.22 Gbps @ 30.7 Kgates for the high-speed version. There is only a slight difference between the performances with and without error detection. The performance overhead caused by the error detection is evaluated at the optimal balance between size and speed and was estimated to be 14.5% at maximum. Conversely, the AES hardware with the proposed scheme had better performance in some cases. If pipeline operation is allowed, as in the CTR mode, throughputs can easily be boosted by further dividing the sub-blocks. Although the proposed error detection scheme was applied to AES in the present study, it can also be applied to other algorithms efficiently.

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Improved differential fault attack against SIMECK based on two-bit fault model

Wan,

Zhang,

et al. 2023

Microelectronics Journal

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Concurrent error detection of fault-based side-channel cryptanalysis of 128-bit RC6 block cipher

Cited by 5 publications

References 10 publications

Delay Insensitive Ternary CMOS Logic for Secure Hardware

Delay Insensitive Ternary CMOS Logic for Secure Hardware

High-Performance Concurrent Error Detection Scheme for AES Hardware

Improved differential fault attack against SIMECK based on two-bit fault model

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