Concurrent Error Detection Adder Based on Two Paths Output Computation

Khedhiri, Chiraz; Karmani, Mouna; Hamdi, Belgacem; Man, Ka Lok

doi:10.1109/ispaw.2011.63

Cited by 15 publications

(4 citation statements)

References 8 publications

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“…are summed up to get the features at a glance. Here on Time Redundant design approach deals with fault detection by executing the same operation on two circuits which are identical and at times by adding latency in the input feed of one of the circuits and compare the output thus obtained, where the same output represents no fault and the difference of output represents a defaulted circuit [1]. The Hardware Redundancy design approach requires multiple instances (two, three or more) of the identical circuits with common input feed giving out different results [2].…”

Section: Existing Fault-tolerant Circuit Designs Approachmentioning

confidence: 99%

“…Introduction I NIn the real-time circuits, it is crucial to identify faults else the outcome may be catastrophic for the system and may even claim human lives too. While designing circuits for these applications, fault detection and fault correction have played a crucial role and posed challenges [1]. As Moore's Law states, "The number of transistors in dense integrated circuit doubles every two years", and hence leads to the growth of complexity.…”

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confidence: 99%

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A Full Adder Design with CNFETs for Real Time, Fault Tolerant and Mission Critical Applications

Srinivasulu¹,

Saini²,

Kumawat³

2020

ELS

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The VLSI based circuits often pose challenges in the form of various faults (such as transient faults, permanent faults, stuck-at-faults). These faults appear even after testing also. They occur because of reduction in the size of the circuit or during realtime implementation, as these faults are difficult to detect. It is very important to detect and rectify all such faults to make the system foolproof and achieve expected functionality. In this paper, 12 transistors based, full adder circuit (12T-FAC) using Carbon Nanotube Field Effect Transistor (CNFET) technology is proposed. The proposed design based on CNFET provides high fault resistance towards transient, permanent faults and works with least power, delay and power-delay product (PDP). Later, features like fault detection and correction circuit have been added in 12T-FAC. The final version of full adder circuit capable of correcting errors has been used in designing applications like multipliers. The proposed full adder circuit was designed with CNFET technology, simulated at 32 nm with supply voltage +0.9 V using the Cadence Virtuoso CAD tool. The model used is Stanford PTM.

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Section: Existing Fault-tolerant Circuit Designs Approachmentioning

confidence: 99%

mentioning

confidence: 99%

A Full Adder Design with CNFETs for Real Time, Fault Tolerant and Mission Critical Applications

Srinivasulu¹,

Saini²,

Kumawat³

2020

ELS

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“…Authors in [22] also proposed a fault detectable adder based on the concept of time redundancy. This design reduces the area overhead and cost of the design by performing the similar operation at different interval of time.…”

Section: Time Redundancymentioning

confidence: 99%

“…The major drawback of this approach is that it requires more than 200% area overhead and cannot detect double fault at a time [22]. The second problem is that fault recovery is not possible because it is not able to detect the faulty module.…”

Section: Double-modular Redundancy (Dmr)mentioning

confidence: 99%

Real-time fault tolerant full adder design for critical applications

Kumar

Sharma

2016

Engineering Science and Technology, an International Journal

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a b s t r a c tIn the complex computing system, processing units are dealing with devices of smaller size, which are sensitive to the transient faults. A transient fault occurs in a circuit caused by the electromagnetic noises, cosmic rays, crosstalk and power supply noise. It is very difficult to detect these faults during offline testing. Hence an area efficient fault tolerant full adder for testing and repairing of transient and permanent faults occurred in single and multi-net is proposed. Additionally, the proposed architecture can also detect and repair permanent faults. This design incurs much lower hardware overheads relative to the traditional hardware architecture. In addition to this, proposed design also provides higher error detection and correction efficiency when compared to the existing designs. Ó 2016 The Authors. Publishing services by Elsevier on behalf of Karabuk University. This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/).

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