Concurrent error detectable and self-repairable carry select adder

Musala, Sarada; Neelam, Aruna Kumari; Sreenivasulu, Bharath; Vardhan, K. Vijaya

doi:10.1080/00207217.2021.2001862

Cited by 11 publications

(5 citation statements)

References 25 publications

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“…Drawing inspiration from biological entities that mend their own wounds, self-repairable structures are designed to autonomously repair damage, restoring their original functionality, and obviating the need for external interventions. The self-repair mechanisms embedded within these materials can be activated when damage is detected, ensuring minor damages do not escalate into major structural problems [32].…”

Section: Self-repairable Structures: Concepts and Applicationsmentioning

confidence: 99%

Emerging Trends in Damage Tolerance Assessment: A Review of Smart Materials and Self-Repairable Structures

Firoozi,

Firoozi

2024

SDHM

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The discipline of damage tolerance assessment has experienced significant advancements due to the emergence of smart materials and self-repairable structures. This review offers a comprehensive look into both traditional and innovative methodologies employed in damage tolerance assessment. After a detailed exploration of damage tolerance concepts and their historical progression, the review juxtaposes the proven techniques of damage assessment with the cutting-edge innovations brought about by smart materials and self-repairable structures. The subsequent sections delve into the synergistic integration of smart materials with self-repairable structures, marking a pivotal stride in damage tolerance by establishing an autonomous system for immediate damage identification and self-repair. This holistic approach broadens the applicability of these technologies across diverse sectors yet brings forth unique challenges demanding further innovation and research. Additionally, the review examines future prospects that combine advanced manufacturing processes with data-centric methodologies, amplifying the capabilities of these 'intelligent' structures. The review culminates by highlighting the transformative potential of this union between smart materials and self-repairable structures, promoting a sustainable and efficient engineering paradigm.

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Section: Self-repairable Structures: Concepts and Applicationsmentioning

confidence: 99%

Emerging Trends in Damage Tolerance Assessment: A Review of Smart Materials and Self-Repairable Structures

Firoozi,

Firoozi

2024

SDHM

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“…A 4-bit and 8-bit PCSA design with less delay and a smaller number of transistors has been presented in this paper [16]. The proposed design and Existing design results are compared and are presented in Table 7 [21]. The real-time schematics of the half adder and Excess-1 circuit are shown in Figure 7 and Figure 9 respectively and the real-time schematic of the 4-bit PCSA is shown in Figure 11 which is implemented using the Cadence Virtuoso tool.…”

Section: Simulation Set-upmentioning

confidence: 99%

A new Excess-1 circuit based High-Speed Carry Select Adder in 18 nm FinFET Technology

Battini

PASHYA

Sivani

2023

Preprint

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Conventional carry select adder (CCSA) uses a multiplexer in the final stage to select either an excess-1 result or a normal result. To improve the delay and number of transistors a new topology is Proposed (PCSA) that uses only a single type of cell i.e., a 2 − 1 multiplexer. The 2 − 1 multiplexer is constructed in CMOS and TGL logic styles using 18nm FinFETs. The sub-blocks such as half adder and excess-1 circuit used in this PCSA is realized using only a 2:1 multiplexer. Due to the usage of a single type 2:1 multiplexer, the PCSA exhibits better circuit regularity. The new topology of PCSA is designed using FinFET-based TGL and CMOS styles. All the adders such 4- and 8-bit are designed, simulated, and analyzed using Cadence Virtuoso, ADEL, and ADEXL at 18nm FinFET technology. The result analysis reveals that the speed performance and the number of transistors of 8-bit PCSA are better by 44.02% and 4% respectively compared to existing adders.

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“…1 The downscaling of the transistor revolutionized the technology industry so that the performance and usage of semiconductor devices increased rapidly. 2 Reducing the physical size of the transistor offered benefits in terms of portability, lower power consumption, and increased speed of the device. 3,4 For every technology node, the physical size of the transistor gets decreasing.…”

mentioning

confidence: 99%

Impact of Scaling on Nanosheet FET and CMOS Circuit Applications

Neelam

Sreenivasulu

Pothupogu

2023

ECS J. Solid State Sci. Technol.

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The impact of scaling on the gate all around the nanosheet field effect transistor (NSFET) was studied in detail at sub-5-nm nodes for digital and analog/RF applications. When LG is scaled from 20 to 5 nm, ION is improved by 2.1×, IOFF increases by three orders of magnitude, SS increases by 27%, DIBL is increased by 4×, and a Vth roll off of 41 mV is noticed. Further, an enhancement of 3.65× was noticed in cut-off frequency (fT) with scaling of LG from 20 to 5 nm. The complimentary metal oxide semiconductor (CMOS) inverter and ring oscillator’s performance was studied in detail with LG scaling. With LG scaling from 20 to 5 nm, the inverter performance metrics like switching current is increased by 3.87×, propagation delay (τP), energy delay product and power delay product are reduced by 65%, 5.5× and 1.95×, respectively. Moreover, the ring oscillator offers superior performance with an oscillation frequency of 98.05 GHz when LG is scaled to 5nm, which is 157% more than fOSC at LG of 20 nm. Thus the analyses reveal the scaling capability of NSFET at both device and circuit levels for sub-5-nm nodes.

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Concurrent error detectable and self-repairable carry select adder

Cited by 11 publications

References 25 publications

Emerging Trends in Damage Tolerance Assessment: A Review of Smart Materials and Self-Repairable Structures

Emerging Trends in Damage Tolerance Assessment: A Review of Smart Materials and Self-Repairable Structures

A new Excess-1 circuit based High-Speed Carry Select Adder in 18 nm FinFET Technology

Impact of Scaling on Nanosheet FET and CMOS Circuit Applications

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