2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA) 2014
DOI: 10.1109/hpca.2014.6835951
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Concurrent and consistent virtual machine introspection with hardware transactional memory

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Cited by 40 publications
(15 citation statements)
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“…It also address the significant challenges of recovery of volatile memory of the virtual machine. Liu et.al [27] proposed an approach called TxIntro that leverage the Hardware Transactional Memory (HTM) for concurrent, consistent and timely introspection of guest operating system by actively monitoring critical kernel data structure of the monitored system. Hizver et.al [18] proposed real-time kernel data structure monitoring (RTKDSM) system of VM that simplifies and automate the analysis of execution state of virtual machine.…”
Section: Related Workmentioning
confidence: 99%
“…It also address the significant challenges of recovery of volatile memory of the virtual machine. Liu et.al [27] proposed an approach called TxIntro that leverage the Hardware Transactional Memory (HTM) for concurrent, consistent and timely introspection of guest operating system by actively monitoring critical kernel data structure of the monitored system. Hizver et.al [18] proposed real-time kernel data structure monitoring (RTKDSM) system of VM that simplifies and automate the analysis of execution state of virtual machine.…”
Section: Related Workmentioning
confidence: 99%
“…Concurrent modifications to data in a read or write set from different threads cause a transaction to abort. The size of the read set, i.e., all memory locations read inside a transaction, appears to be limited by the size of the L3 cache, and the size of the write set, i.e., all memory locations modified inside a transaction, appears to be limited by the size of the L1 cache [32].…”
Section: Applicationmentioning
confidence: 99%
“…3.4. In more distant security-related research, Liu et al [34] demonstrated the use of Intel TSX to facilitate virtual machine introspection. Guan et al [19] explored the use of TSX to protect cryptographic keys in CPU caches to prevent memory disclosure attacks.…”
Section: Transactional Synchronization Extensionsmentioning
confidence: 99%
“…In terms of usability of Intel TSX, it has been shown in these prior studies [34,19] that enclosing large code regions inside TSX transactions may induce numerous transaction aborts, degrading the performance of their applications and even making it unusable. Our use of Intel TSX avoids such issues by only enclosing a small loop inside the transaction, which significantly reduces the likelihood of transaction aborts due to regular system operations.…”
Section: Transactional Synchronization Extensionsmentioning
confidence: 99%