Concept of the First Level Global Trigger for the CMS experiment at LHC

Abstract

The requirements, the principles and the design of the First Level Global Trigger Processor of the CMS experiment under construction at the CERN Large Hadron Collider are described. A trigger decision based on trigger objects delivered by the detector subsystems is provided for each beam crossing at a rate of 40 MHz. The Global Trigger comprises a novel concept where event selection is not only based on objects exceeding energy or momentum thresholds but also on complex event topology, which is made possible by the availability of space, charge and quality information in the algorithm calculations. The trigger logic is largely programmable in order to satisfy all possible physics requirements.

Modular Design of High-Throughput, Low-Latency Sorting Units

“…The difference in the number of CAE blocks between bitonic and odd-even merge sorting units is 2 n−1 × (n − 2) + 1, which shows that the difference in the number of CAE blocks increases linearly with the number of inputs. For example, in the Large Hadron Collider [35], built by the European Organization for Nuclear Research (CERN), low-latency max-set-selection units identify important particle interactions that correspond to high-energy collisions [18,55]. In multimedia applications, partial sorting units speed up data sorting algorithms [17].…”

“…For most applications, the sorting unit outputs only the top four objects. For example, the CMS Global Calorimeter trigger (GCT) [52,54,55] sorts the candidate electrons, photons, taus, and jets and forwards the four most energetic objects of each type to the Global trigger. Based on the values of these sorted objects and other factors, a decision is made to keep or discard data produced by the CMS Experiment during a specified time interval.…”

“…Sorting is an important operation in a wide range of applications including data mining, databases [7,19,31], digital signal processing [47,48], network processing, communication switching systems [4,58], scientific computing [15], searching, scheduling [51], pattern recognition, robotics [10], image and video processing [11,12,17,49], and high-energy physics (HEP) [23,55]. For applications that require very high-speed sorting, hardware sorting units are often implemented using either ASICs or FPGAs to meet performance requirements [13,28,31,33,38,41,49].…”

Implementation and synchronisation of the First Level Global Trigger for the CMS experiment at LHC

“…Missing and total transverse energies consist of 12 bits, whereas the numbers of jets above thresholds are represented as 4 bits. The detailed description of all bits is given in [4].…”

“…These rules are implemented in the logic of the Trigger Control System (TCS) and have to be set such that the overall dead time stays below the order of 1 percent. The concept of the CMS Level-1 Global Trigger is described in detail in [4].…”