Computing Meets Network: COIN-Aware Offloading for Data-Intensive Blind Source Separation

Wu, Huanzhuo; Zuo, Xiang; Nguyen, Giang; Shen, Yunbin; Fitzek, Frank H. P.

doi:10.1109/mnet.011.2100060

Cited by 11 publications

(8 citation statements)

References 6 publications

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“…We note that the different forms of software entities can be physically executed in any computing location in communication networks [76], such as in-network computing [77]- [79] also referred to as computing in the network (COIN) [80], fog computing [81], [82], and multi-access edge computing (MEC) [83]- [89].…”

Section: E Summary Of Nf Softwarizationmentioning

confidence: 99%

Operating Systems and Hypervisors for Network Functions: A Survey of Enabling Technologies and Research Studies

et al. 2022

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Scalable and flexible communication networks increasingly conduct the packet processing for Network Functions (NFs) in General Purpose Computing (GPC) platforms. The input/output (I/O)-intensive and latency-sensitive packet processing is challenging for the operating systems and hypervisors running on GPC platforms. This article surveys the existing enabling technologies and research studies on operating system and hypervisor aspects that directly influence the packet processing for NFs on GPC platforms. We organize this survey according to the main categories abstraction approach, memory access, and I/O strategy. We further categorize abstraction approach technologies and research studies into the categories operation systems, hypervisors, and containers. We partition the memory access category into the two subcategories of memory allocation and memory access, while we partition the I/O strategy category into the sub-categories I/O device virtualization and I/O device access. Our survey gives a comprehensive summary of the capabilities and limitations of the existing enabling technologies and researched approaches for abstraction, memory access, and I/O for NF packet processing. We outline critical future research directions for advancing NF packet processing on GPC platforms.

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Section: E Summary Of Nf Softwarizationmentioning

confidence: 99%

Operating Systems and Hypervisors for Network Functions: A Survey of Enabling Technologies and Research Studies

et al. 2022

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“…Modern wireless communication systems operate at a data rate of hundreds of megabits per second [16]- [18] with complex-valued signals. Furthermore, IoT applications usually require strict real-time processing [7], [8]. Therefore, it is crucial to design a high-throughput ICA preprocessor for these systems.…”

Section: B Related Workmentioning

confidence: 99%

“…For example. the diagonalization of the four 2 × 2 submatrices (1, 2), (3,4), (5,6), (7,8) are conducted in parallel in ordering 1.…”

Section: B Evd Processing Sequencementioning

confidence: 99%

“…of each transmitted signal in cognitive radio (CR) system [6]. Recently, it is proposed in [7], [8] that ICA can be used in a temporal-critical industrial internet of things (IoT) application for anomaly detection or identification. A common theme of these previous use cases is that the source signals are expected to be extracted in real-time thus demanding high-performance ICA architectures.…”

Section: Introductionmentioning

confidence: 99%

“…A common drawback of many ICA preprocessors described in the literature is that they only support real-valued signals and operate at low processing speeds. However, new applications of ICA in use cases such as wireless communications [16]- [18] where high data rates, latency-sensitive [7], [8], complex-valued samples are common demand novel, high throughput ICA architectures.…”

Section: Introductionmentioning

confidence: 99%

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Configurable Independent Component Analysis Preprocessing Accelerator

Shen

Fouda

et al. 2022

IEEE Trans. VLSI Syst.

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Independent component analysis (ICA) has been used in many applications, including self-interference cancellation for in-band full-duplex wireless systems and anomaly detection in industrial internet of things. This paper presents a high-throughput and highly efficient configurable preprocessing accelerator for the ICA algorithm. The proposed ICA accelerator has three major blocks that perform data centering, covariance matrix for computation, and eigenvalue decomposition (EVD). Specifically, the proposed accelerator is based on a high-performance matrix multiplication array (MMA). The proposed MMA architecture uses time-multiplexed processing so that the efficiency of hardware utilization is greatly enhanced. Furthermore, the processing flow utilizes parallel processing such that the centering, the calculation of the covariance matrix, and EVD are conducted simultaneously and are individually pipelined to maximize throughput. This paper presents the architecture, circuit design, and performance estimates based on post-layout extraction of the proposed preprocessing ICA accelerator. The proposed design achieves a throughput of 40.7 kMatrices per second at complexity of 73.3 kGE.

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Fast IMU-based Dual Estimation of Human Motion and Kinematic Parameters via Progressive In-Network Computing*

Dai,

Wu,

Wang

et al. 2023

IFAC-PapersOnLine

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Computing Meets Network: COIN-Aware Offloading for Data-Intensive Blind Source Separation

Cited by 11 publications

References 6 publications

Operating Systems and Hypervisors for Network Functions: A Survey of Enabling Technologies and Research Studies

Operating Systems and Hypervisors for Network Functions: A Survey of Enabling Technologies and Research Studies

Configurable Independent Component Analysis Preprocessing Accelerator

Fast IMU-based Dual Estimation of Human Motion and Kinematic Parameters via Progressive In-Network Computing*

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