Computerised Gate Firing Control for 17-Level MLI using Staircase PWM

Abstract

A basic 7-level MLI topology is developed and the same is extended to the 9-level then further increased to 17-levels. The developed structure minimizes the component's count and size to draw out the system economy. Despite the various advantages of MLIs, efficiency and reliability play a major role since the usage of components is higher for getting a low Total Harmonics Distortion (THD) value. This becomes a major challenge incorporated in boosting the efficiency without affecting the THD value. Various parametric observations are done and realized for the designed 9-level and 17-level MLI, being the Total Standing Voltage (TSV), efficiency, cost function per level count, and power loss. The respective parameters are compared with several existing and modern circuits and found to be effective in their performance. A novel single-phase 17-level asymmetrical Multi-Level Inverter (MLI) topology is developed to reduce the number of overall components. The developed topology generates 17-levels by using unequal DC sources. The developed MLI is proved under various tests conducted experimentally for the various loads like resistive, inductive, and combinational loads. A detailed comparison is done on several factors and represented graphically represented. Further, the proposed design provides a less TSV value is 6 V dc , efficiency is 94.21% and cost factor per level CF/L value for both values of α is 2.01 and 2.05 and devices count with a low THD value 41.4% with respectively.