Computer generation of fast fourier transforms for the cell broadband engine

Abstract

The Cell BE is a multicore processor with eight vector accelerators (called SPEs) that implement explicit cache management through direct memory access engines. While the Cell has an impressive floating point peak performance, programming and optimizing for it is difficult as it requires explicit memory management, multithreading, streaming, and vectorization. We address this problem for the discrete Fourier transform (DFT) by extending Spiral, a program generation system, to automatically generate highly optimized implementations for the Cell. The extensions include multi-SPE parallelization and explicit memory streaming, both performed at a high abstraction level using rewriting systems operating on Spiral's internal domain-specific language. Further, we support latency and throughput optimizations, single and double precision, and different data formats. The performance of Spiral's computer generated code is comparable with and sometimes better than existing DFT implementations, where available.

An FFT Performance Model for Optimizing General-Purpose Processor Architecture

“…Besides, to explore the performance per Watt, we define a measure as data-rate-per-Watt ψ for an N -point FFT: ψ = N/t/p (samples/µs/W) = N/(t × p) (samples/µJ). (27) ψ represents the processing rate per Watt (samples/µs/W), as well as the samples processed per energy (samples/µJ). To achieve higher performance per Watt, the FFT implementation should have higher ψ.…”

“…The 3.2 GHz Cell BE [27] contains one traditional PowerPC core and eight SIMD vector cores (SPEs) with 128-bit vector support. Each SPE has the fast on-chip 256 KB local memory, and data transfer between the intercore and memory-local core is performed via DMA.…”

Multi-FFT Vectorization for the Cell Multicore Processor

“…But operations on words of lengths of up to 512 bits had also been proposed (e.g., on the CDC STAR-100). In recent years, with the emergence of SIMD-enhanced multicore devices with short vector instructions (up to 128 bits), there is a rapidly increasing interest in the topic [12][13][14][15]. Most of the latest reported innovations attempt to achieve optimal device-dependent performance by optimizing cache utilization or vectorizing operations carried out on a single data sequence.…”

“…The Cell architecture is illustrated in Figure 1. Further details on the design parameters of the PXC 8i are well documented [14][15][16] and will not be repeated here. Note that both FORTRAN 95/2003 and C/C++ compilers for multi-core acceleration under Linux (i.e., XLF and XLC) are provided by IBM.…”

Discrete fourier transform on multicore

“…OpenCL [44] is an emerging open standard for parallel programming of heterogeneous systems; one of its targets is GPU computing and partitioning of computation across CPUs and GPUs.…”