Computer‐aided design methodology for linearity enhancement of multiwatt GaN HEMT amplifiers using multiple parallel devices

Abstract

This article presents a design methodology for linearizing GaN HEMT amplifiers based on splitting a large FET into multiple parallel FETs with same total gate periphery and by biasing them individually. By varying the biases, the magnitude and the phase of the IMD3 components at the output of FET changes. A detailed simulation methodology using commercial microwave CAD software is presented. Simulation results show that by biasing one device in Class AB and other(s) in deep Class AB mode, IMD3 components of parallel FETs can be made out of phase to each other leading to cancellation and improvement in linearity. Three prototype circuits were simulated using (a) a single 5 mm FET (1 × 5 mm), (b) two parallel 2.5 mm FETs (2 × 2.5 mm), and (c) four parallel 1.25 mm FETs (4 × 1.25 mm), for a total gate periphery of 5 mm, over the frequency range of 0.8 to 1.0 GHz. IMD3 improvement up to 20 dBc was achieved with the 4 × 1.25 mm circuit when the FET biases were optimized. Measurement results show improvement in linearity up to 20 dBc for 4 × 1.25 mm circuit. The proposed method improves linearity without a substantial penalty on the power consumption and is straightforward to implement. K E Y W O R D Sgallium nitride, IMD3, linearization, nonlinearity, phase cancellation, power amplifier

Simulation of a Parallel Dual‐Metal‐Gate Structure for AlGaN/GaN High‐Electron‐Mobility Transistor High‐Linearity Applications

“…The design of a linear PA using different gate bias voltages for parallelly combined GaN HEMTs has been presented. [26,27] V gs of each subunit was adjusted independently, and the total power consisted of all subcell outputs. Considering the different g m values of the device under different V gs , the total g m can remain linear in the output power range and reduce IMD3.…”

A power amplifier with bandwidth expansion and linearity enhancement in 130 nmcomplementary metal‐oxide‐semiconductorprocess

“…8,9 Optimization of the nonlinear transconductance technique is introduced to reduce the intermodulation distortions, but IMD behavior is sensitive to the bias voltage and input power level. 10,11 Multiple-gated transistor (MGTR) technique can cancel out the odd-order intermodulation and harmonic distortions in a more robust way, [12][13][14][15] but the second harmonic distortion increases. In this work, MGTR technique is used and a π network is adopted to suppress the harmonic distortions.…”