Computationally-redundant energy-efficient processing for y'all (CREEPY)

Deng, Bobin; Srikanth, Sriseshan; Hein, Eric R.; Rabbat, Paul G.; Conte, Thomas M.; DeBenedictis, Erik P.; Cook, Jeanine

doi:10.1109/icrc.2016.7738714

Cited by 9 publications

(7 citation statements)

References 5 publications

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“…The big selling point of RRNS is that the energy required to multiply n-bit numbers scales approximately linearly in n, rather than quadratically as in the usual binary number representations. Our student collaborators in Tom Conte's group at Georgia Tech have made great strides in designing and simulating RRNS-based architectures [8]. So definitely, I agree there is still some useful progress to be made at the architectural level, even independently of reversible computing.…”

Section: Mfmentioning

confidence: 99%

Art Scott and Michael Frank on energy-efficient computing

Lewis¹

2017

Ubiquity

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Editor's IntroductionClock speeds of computing chips have leveled off dramatically since 2005, and putting more cores in systems on a chip (SoC) has produced more heat, adding a new ceiling to further advances. Leading-edge researchers, like Mike Frank, and dedicated technologists with a wealth of experience, like Art Scott, represent a new vanguard of the leap-forward beyond Dennard scaling and Landauer's limit. Art looks for ways to reduce energy consumption and Mike looks for ways to "architect" future chips according to principles of reversibility. Is the future in reversible, adiabatic computing and simpler architectures using posit arithmetic? My guests think so.Ted Lewis: You have been in the computing industry for a long time, going all the way back to the beginning of Moore's law. Generally speaking, you have participated in making computers run faster and hotter, but since around 2005 Moore's law has hit a wall because of heat-the end of Dennard scaling has forced chip-makers to face the problem of heat dissipation. As a consequence, clock speeds have not improved for a decade, see Figure 1. Some say the answer is reversible computing. What is reversible computing and how did you become interested in it?Art Scott: Energy efficient is the answer to Landauer's limit, the act of erasing a bit of information gives off an amount of heat related to the temperature and Boltzmann's constant-a total of 3×10 -21 joules at room temperature. Reversible computing is energy efficient; therefore, reversible computing is the answer to Landauer's limit. Your readers can find out more online where Wikipedia describes the reason reversible computing is now center stage, "Probably the largest motivation for the study of technologies aimed at actually implementing reversible computing is that they offer what is predicted to be the only potential way to improve the computational energy efficiency of computers beyond the fundamental von Neumann-Landauer limit of kT ln 2 energy dissipated per irreversible bit operation." 1 There, k is the Boltzmann constant (approximately 1.38×10 −23 J/K), T is the absolute temperature of the environment, and ln 2 is the natural logarithm of 2 (approximately 0.69315). Reversible means the computation can be reversed, in other words, the inputs can be obtained from the outputs, by running circuits backwards. However, the purpose of reversible design is not to run backwards, but to avoid heat generation associated with increased thermodynamic entropy,

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Section: Mfmentioning

confidence: 99%

Art Scott and Michael Frank on energy-efficient computing

Lewis¹

2017

Ubiquity

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“…For example, it is known that the Residue Number System (RNS) [32] can help distribute contiguous data to a wider range [25,26,73]. Such a hash function would be computed by concatenating the set of residues (moduli) R(κ) of key κ against a pre-determined set of co-prime bases B such that R(κ) = {κ%b, b ∈ B}.…”

Section: Tree Partitioningmentioning

confidence: 99%

MetaStrider

Srikanth

Jain

Lennon

et al. 2019

ACM Trans. Archit. Code Optim.

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Reduction is an operation performed on the values of two or more key-value pairs that share the same key. Reduction of sparse data streams finds application in a wide variety of domains such as data and graph analytics, cybersecurity, machine learning, and HPC applications. However, these applications exhibit low locality of reference, rendering traditional architectures and data representations inefficient. This article presents MetaStrider, a significant algorithmic and architectural enhancement to the state-of-the-art, SuperStrider. Furthermore, these enhancements enable a variety of parallel, memory-centric architectures that we propose, resulting in demonstrated performance that scales near-linearly with available memory-level parallelism.

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“…Therefore, the X RRNS value is the the RRNS of 106 and Y RRNS value is the the RRNS of 209. We observe that the pair (Δm 5 , Δm 6 ) remains at a fixed value (10,11). (2) Add two negative numbers.…”

Section: Signed Number Overflow Detection Recall From Section 43 Thmentioning

confidence: 99%

“…From an independent set of simulations of a non-error-correcting core operating on binary data, we find that the minimal signal energy required for ensuring its reliable operation is 48kT. In our previous design of an error correcting RRNS core [11], we assumed a single voltage domain across computational logic, SRAM cells, and RIU logic. Together with a traditional multiplier (i.e., without index-sum), a pipelined check insertion strategy (with a frequency of five instructions) and a 16MB LLC, the result is that we can tolerate gate signal energies of 42-43kT, as shown in Figure 8.…”

Section: Signal Energy Limitsmentioning

confidence: 99%

“…RRNS_pipe5. An error correcting RRNS core with a pipelined check insertion strategy (with a frequency of five instructions), as was determined as the most optimal strategy in our previous RRNS core design [11]. For example, 30-43-48 denotes the gate signal energy for computational logic to be 30kT, SRAM cells to be 43kT, and RIU logic to be 48kT.…”

Section: Signal Energy Limitsmentioning

confidence: 99%

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Extending Moore’s Law via Computationally Error-Tolerant Computing

Deng

Srikanth

Hein

et al. 2018

ACM Trans. Archit. Code Optim.

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Dennard scaling has ended. Lowering the voltage supply (V dd) to sub-volt levels causes intermittent losses in signal integrity, rendering further scaling (down) no longer acceptable as a means to lower the power required by a processor core. However, it is possible to correct the occasional errors caused due to lower V dd in an efficient manner and effectively lower power. By deploying the right amount and kind of redundancy, we can strike a balance between overhead incurred in achieving reliability and energy savings realized by permitting lower V dd. One promising approach is the Redundant Residue Number System (RRNS) representation. Unlike other error correcting codes, RRNS has the important property of being closed under addition, subtraction and multiplication, thus enabling computational error correction at a fraction of an overhead compared to conventional approaches. We use the RRNS scheme to design a Computationally-Redundant, Energy-Efficient core, including the microarchitecture, Instruction Set Architecture (ISA) and RRNS centered algorithms. From This paper is an extension of "Computationally-Redundant Energy-Efficient Processing for Y'all (CREEPY)" [11]. This submission adds the following: (1) Correction factor analysis for RRNS signed arithmetic, including an improved correction factor computation for signed multiplication via an LUT based mechanism. (Section 4.8.5) (2) Design and evaluation of an efficient RRNS multiplier unit by using the index-sum technique, along with associated re-derivation of suitable RRNS bases. (Sections 4.4 and 4.5) (3) A novel adaptive check insertion strategy that leverages hardware/software runtime or compiler. (Section 4.6.3) (4) Impact of multi-domain voltage supply to further lower energy consumption. (Sections 4.7, 6.1 and 6.3) (5) Improved evaluation accuracy by simulating an LLC-main memory hierarchy instead of a perfect cache. (Section 5) (6) Energy limit analysis for binary, RNS and RRNS cores. (Section 6) These add significantly more than 30% new material and provide greater insight into RRNS core design. W.r.t. written content, every section has been revamped to better present the new findings above.

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Computationally-redundant energy-efficient processing for y'all (CREEPY)

Cited by 9 publications

References 5 publications

Art Scott and Michael Frank on energy-efficient computing

Art Scott and Michael Frank on energy-efficient computing

MetaStrider

Extending Moore’s Law via Computationally Error-Tolerant Computing

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