Computationally Minimized X-Part for FX Correlator in Big-Data Interferometers

Research on Digital Correlator Algorithm Based on FPGA

“…Table II shows the state of the storage of eight data in address 0, in which x[0] to x [7] and y[0] to y [7] are both signed numbers of 12bit, and the storage state in other addresses is similar to this. [1] x [2] x [3] x [4] x [5] x [6] x [7] RAM2 After sampling, correlation operations are started, use Quartus II as software platform and Verilog HDL language. The adopted FPGA belongs to the series of CYCLONE IV, and the model is EP4CE15F23C8.…”

“…Its powerful ability to suppress noise makes it extremely widely used in the field of signal processing [1]. The main application fields include the signal processing of radar signal receiver [2], [3], accurate positioning by measuring the delay difference of the same signal, the synchronization of the communication system by correlation between the receiving sequence and the local sequence, the decision of the signal in the direct sequence spread spectrum communication and the restoration of the original signal, and the application of the GPS receiver [4].…”

Low‐complexity architecture for AR(1) inference

“…Hardware implementation: The ACF, Kedem, and the proposed approximate estimator were implemented on a Xilinx Artix-7 XC7A35T-1CPG236C FPGA device. Although there are different architectures for digital correlators based on fast Fourier transforms (FFTs) for different applications [16], we choose not to implement such scheme given its higher complexity in terms of resources and power compared to the architecture in Fig. 2.…”