Computationally Efficient Neural Feature Extraction for Spike Sorting in Implantable High-Density Recording Systems

Kamboh, Awais Mehmood; Mason, Andrew J.

doi:10.1109/tnsre.2012.2211036

Cited by 77 publications

(64 citation statements)

References 25 publications

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“…If all the detected spikes need to be wirelessly transmitted for offline feature-extraction and clustering, the power can be prohibitive [4] [5]. Online feature extraction and clustering have been shown to significantly reduce the required data rate for wireless communication, resulting in large energy savings in the system level [6].…”

Section: Fig 1: a General Brain-computer Interface Operation Flowchartmentioning

confidence: 99%

A low power unsupervised spike sorting accelerator insensitive to clustering initialization in sub-optimal feature space

Jiang

Wang

Seok

2015

Proceedings of the 52nd Annual Design Automation Conference

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Online unsupervised spike sorting or clustering is an integral component of implantable closed-loop brain-computer-interface systems. Robust clustering performance against various nonidealities such as poor initialization and order-of-arrival of inputs are desirable while meeting the minimal area and power requirements for implants. We explore an online and unsupervised spike-sorting algorithm utilizing a low-overhead feature screening process that improves feature discriminability in the use of suboptimal features for reducing hardware complexity. Based on the algorithm, an accelerator architecture that performs feature screening and clustering is devised and implemented in a 65-nm high-V TH CMOS, largely improving clustering accuracy even with poor clustering initialization. In the post-layout static timing and power simulation, the power consumption and the area of the accelerator are found to be 2.17 μW/ch and 0.052 μm 2 /ch, respectively, which are 53% and 25% smaller than the previous designs, while achieving the required throughput of 420 sorting/s at the supply voltage of 300mV.

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Section: Fig 1: a General Brain-computer Interface Operation Flowchartmentioning

confidence: 99%

A low power unsupervised spike sorting accelerator insensitive to clustering initialization in sub-optimal feature space

Jiang

Wang

Seok

2015

Proceedings of the 52nd Annual Design Automation Conference

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“…Alternatives to PCA and GHA include techniques such as discrete derivatives [12,13], integral transform [14] and zero-crossing [15] for feature extraction. The techniques feature low computational costs without additional training procedures.…”

Section: Introductionmentioning

confidence: 99%

A Low Cost VLSI Architecture for Spike Sorting Based on Feature Extraction with Peak Search

Chang

Hwang

Chen

2016

Sensors

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The goal of this paper is to present a novel VLSI architecture for spike sorting with high classification accuracy, low area costs and low power consumption. A novel feature extraction algorithm with low computational complexities is proposed for the design of the architecture. In the feature extraction algorithm, a spike is separated into two portions based on its peak value. The area of each portion is then used as a feature. The algorithm is simple to implement and less susceptible to noise interference. Based on the algorithm, a novel architecture capable of identifying peak values and computing spike areas concurrently is proposed. To further accelerate the computation, a spike can be divided into a number of segments for the local feature computation. The local features are subsequently merged with the global ones by a simple hardware circuit. The architecture can also be easily operated in conjunction with the circuits for commonly-used spike detection algorithms, such as the Non-linear Energy Operator (NEO). The architecture has been implemented by an Application-Specific Integrated Circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture is well suited for real-time multi-channel spike detection and feature extraction requiring low hardware area costs, low power consumption and high classification accuracy.

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“…These reduction methods can simply be in the form of data compression but several works have demonstrated hardware implementable feature extraction methods. These includes those based on derivative (Gibson et al, 2008;Paraskevopoulou et al, 2013), templates (Rizk et al, 2009), zero crossings (Kamboh and Mason, 2012) and neuronal spike shape and area (Zviagintsev et al, 2005), to name a few.…”

Section: Introductionmentioning

confidence: 99%

“…Until recently, the consensus was to implement the classification process after transmission because of its high complexity. For this there are a num- (Karkare et al, 2011) 2011 NEO DD -64 2.03 0.09 0.06 (Chen et al, 2012) 2012 NEO DWT/PCA k-means 128 0.68 0.09 0.07 * (Kamboh and Mason, 2012) 2012 DT ZCF Mahalanobis ---- (Karkare et al, 2013) 2013 Abs PP modified k-means 16 4.68 0.065 0.07 * (Saeed and Kamboh, 2013) 2013 NEO ZCF MCK classifier ----*This paper shows the potential of hardware implementation.…”

Section: Introductionmentioning

confidence: 99%

Hierarchical Adaptive Means (HAM) clustering for hardware-efficient, unsupervised and real-time spike sorting

Paraskevopoulou

Eftekhar

et al. 2014

Journal of Neuroscience Methods

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This work presents a novel unsupervised algorithm for real-time adaptive clustering of neural spike data (spike sorting). The proposed Hierarchical Adaptive Means (HAM) clustering method combines centroid-based clustering with hierarchical cluster connectivity to classify incoming spikes using groups of clusters. It is described how the proposed method can adaptively track the incoming spike data without requiring any past history, iteration or training and autonomously determines the number of spike classes. Its performance (classification accuracy) has been tested using multiple datasets (both simulated and recorded) achieving a near-identical accuracy compared to k-means (using 10-iterations and provided with the number of spike classes). Also, its robustness in applying to different feature extraction methods has been demonstrated by achieving classification accuracies above 80% across multiple datasets. Last but crucially, its low complexity, that has been quantified through both memory and computation requirements makes this method hugely attractive for future hardware implementation.

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Computationally Efficient Neural Feature Extraction for Spike Sorting in Implantable High-Density Recording Systems

Cited by 77 publications

References 25 publications

A low power unsupervised spike sorting accelerator insensitive to clustering initialization in sub-optimal feature space

A low power unsupervised spike sorting accelerator insensitive to clustering initialization in sub-optimal feature space

A Low Cost VLSI Architecture for Spike Sorting Based on Feature Extraction with Peak Search

Hierarchical Adaptive Means (HAM) clustering for hardware-efficient, unsupervised and real-time spike sorting

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