Computation of yield-optimized Pareto fronts for analog integrated circuit specifications

Mueller-Gritschneder,; Graeb,

doi:10.1109/date.2010.5456971

Cited by 13 publications

(7 citation statements)

References 13 publications

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“…Therefore, instead of a single solution, multi-objective algorithms provide the trade-off of the multiple objectives represented in the Pareto front [17]. The Pareto front is a set of solution points that can not be improved in one objective without getting degraded in another [13,18]. The general formulation of a constrained optimization problem is as follows: ub , e(x,p) = 0, and g(x,p) < 0.…”

Section: Multi-objective Optimizationmentioning

confidence: 99%

“…Optimization algorithms can be classified in two main categories according to the operations performed to find solutions: deterministic or gradient-based [19,20], and stochastic or heuristicsbased [12,18,[21][22][23]. If a problem has an objective function that allows the calculation of gradients and a search space with a global minimum, using deterministic algorithms is usually the fastest way to find a solution.…”

Section: Multi-objective Optimizationmentioning

confidence: 99%

“…SQP is particularly effective at handling problems with significant non-linearity in their constraints [24], which makes this algorithm well suited for our application, as many analog circuit specifications exhibit non-linear relationships with circuit design parameters. In fact, SQP has been successfully employed previously for circuit automatic design [16,18]. The minimization function in the gradient-based optimization is built as the weighted sum of the optimization functions.…”

Section: Gradient-based Optimization Algorithmsmentioning

confidence: 99%

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Gaussian-Process-Based Surrogate for Optimization-Aided and Process-Variations-Aware Analog Circuit Design

et al. 2020

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Optimization algorithms have been successfully applied to the automatic design of analog integrated circuits. However, many of the existing solutions rely on expensive circuit simulations or use fully customized surrogate models for each particular circuit and technology. Therefore, the development of an easily adaptable low-cost and efficient tool that guarantees resiliency to variations of the resulting design, remains an open research area. In this work, we propose a computationally low-cost surrogate model for multi-objective optimization-based automated analog integrated circuit (IC) design. The surrogate has three main components: a set of Gaussian process regression models of the technology’s parameters, a physics-based model of the MOSFET device, and a set of equations of the performance metrics of the circuit under design. The surrogate model is inserted into two different state-of-the-art optimization algorithms to prove its flexibility. The efficacy of our surrogate is demonstrated through simulation validation across process corners in three different CMOS technologies, using three representative circuit building-blocks that are commonly encountered in mainstream analog/RF ICs. The proposed surrogate is 69 X to 470 X faster at evaluation compared with circuit simulations.

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Section: Multi-objective Optimizationmentioning

confidence: 99%

Section: Multi-objective Optimizationmentioning

confidence: 99%

Section: Gradient-based Optimization Algorithmsmentioning

confidence: 99%

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Gaussian-Process-Based Surrogate for Optimization-Aided and Process-Variations-Aware Analog Circuit Design

et al. 2020

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“…In the literature, many yield-aware synthesis approaches are proposed based on simulation-based techniques [3][4][5][6]. After the device sizes are obtained in each iteration, the design yield is also evaluated while simulating the circuit performance.…”

Section: Introductionmentioning

confidence: 99%

Low-noise analog synthesis platform for bio-signal acquisition system

Lien

Lee

et al. 2015

VLSI Design, Automation and Test(VLSI-Dat)

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Because the bio-signals are often very weak, they can be influenced by noise easily and become hard to distinguish. In this paper, an automatic analog synthesis platform is presented for bio-acquisition systems to generate the required circuits from specification to layout with low-noise consideration. Process variations and layout effects are also simultaneously considered to generate the required circuits with high design yield. Furthermore, a user-friendly GUI is also provided to help users complete the design flow successfully and efficiently. As shown in the experimental results, this analog synthesis platform is able to generate the required circuits in seconds with low noise. The chip implementation result also verifies the capability of this tool to generate the required designs with fabricable quality.

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“…Although the result of the approach might not be the global worst case points, the su±cient accuracy of the method has been shown in previous publications. 7,13 Besides the worst case points, the gradient of the objective function must be computed for the FSQP approach. For this purpose, the sensitivities against variations in the design parameters and the performance values are computed at the approximated worst case points in lines 13À18.…”

Section: Automatic Sizing Approachmentioning

confidence: 99%

Tolerance Design of Analog Circuits Using a Branch-and-Bound Based Approach

Pehl¹,

Graeb²

2012

J CIRCUIT SYST COMP

Self Cite

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The design of circuits which are robust against variations in operating and process conditions is crucial in today's IC industry. In the analog design°ow this problem can be tackled during the sizing of a new circuit. However, hardly any methods are available which support the designer to compute such a robust design if discrete parameters should be considered in this design step. Discrete parameters arise predominantly if a layout-friendly sizing should be computed in the sense that, e.g., a manufacturing grid for the transistor lengths and widths is considered or that transistor multipliers are used to allow the layout of a transistor as multi¯nger or common centroid structure without applying rounding operations to the carefully computed sizing. This paper presents a new Branch-and-Bound based approach which allows the automatic computation of a robust design using classical and realistic worst case analysis. The results of the sizing of three circuits show that the new approach is highly e±cient. The robustness of the results computed by the new approach is validated by Monte Carlo analyses.

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Computation of yield-optimized Pareto fronts for analog integrated circuit specifications

Cited by 13 publications

References 13 publications

Gaussian-Process-Based Surrogate for Optimization-Aided and Process-Variations-Aware Analog Circuit Design

Gaussian-Process-Based Surrogate for Optimization-Aided and Process-Variations-Aware Analog Circuit Design

Low-noise analog synthesis platform for bio-signal acquisition system

Tolerance Design of Analog Circuits Using a Branch-and-Bound Based Approach

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