Computation of Walsh spectrum from binary decision diagram and binary decision diagram from Walsh spectrum

Stigall, Paul D.; Li, X.; Dawson, D.F.

doi:10.1016/0045-7906(89)90010-4

Cited by 5 publications

(6 citation statements)

References 11 publications

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“…The inverse transform is given by [12,27,71,73,74,90,92,[94][95][96][97]. In a disjoint representation of an mv function every minterm is covered only once.…”

Section: ::{)mentioning

confidence: 99%

“…Each spectral coefficient is calculated by the multiplication of a row vector of the transform matrix T and the function vector F, as in Equation (IV.l). This lead to the development of algorithms to compute the Walsh and Reed-Muller spectrum from an arithmetic cover [12,26], disjoint representations [73,75,95,94,97], and the computation of the Arithmetic and Adding spectrum from a minterm representation [90,108].…”

Section: Iv2 Relations Of Specfral Techniques To Classical Logicmentioning

confidence: 99%

“…Rademacher-Walsh, Hademard-Walsh, Kaczmarz-Walsh and Walsh-Paley [65,70,74] exhibit a special property which allows the development of an algorithm for their fast computation from a disjoint representation [73,94]. Similarly to the general calculation method of transforms for mv logic presented in the previous chapter, the algorithms for the calculation of the Rademacher-Walsh spectrum for Boolean functions introduced in [73,94] are based on calculating the value for each spectral coefficient separately. However, the Walsh-type transforms allow a direct two-dimensional mapping of the function in Boolean domain to the RademacherWalsh spectrum.…”

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Orthogonal and Nonorthogonal Expansions for Multi-Level Logic Synthesis for Nearly Linear Functions and their Application to Field Programmable Gate Array Mapping

Schäfer¹

2000

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The growing complexity of integrated circuits and the large variety of architectures of Field Programmable Gate Arrays (FPGAs) require sophi~ticated logic design tools. In 2 the beginning of the eighties the research in logic design was concentrated on the development of fast two-level AND-OR logic minimizers like the well known ESPRESSO. However, most logic functions have a smaller and often faster circuit realization as a multi-level circuit. Thus, synthesis tools emerged for the minimization of the circuit area in a multi-level realization. Most of these synthesis tools are based on the "unate paradigm". Therefore, the synthesis methods are only advantageous for functions having a minimal circuit realization based on AND-OR gates. However, many common functions have a minmal circuit realization having a mix of AND, OR and EXOR gates like counters, adders, multipliers, and parity generators. Therefore, the design of such functions with synthesis tools based on the "unated paradigm" is very inefficient Circuits incorporating the EXOR gate have received less attention than AND-OR circuits because the EXOR gate was perceived as slower and larger in terms of its circuit realization than the AND and the OR gate. However, the upcoming of Field Programmable Gate Arrays (FPGAs) like the Xilinx Table-Look-Up (TLU) architecture the Actel ACT™ series and the CLi 6000 series from Concurrent Logic, which allow the realization of the EXOR gate with the same speed and circuit cost as the AND and OR gate, eliminates the disadvantages of the EXOR gate over the AND and OR gate. Thus, there is a strong need for logic synthesis tools that take advantage of EXOR gates.The mapping to th~new FPGAs recently obtained an increased interest. The developed synthesis algorithms for FPGAs are based on the mapping and restructuring of the Directed Acyclic Graph (DAG) representation of the logic function. Even though the new FPGAs allow the realization of the EXOR gate without any speed and circuit size penalty in comparison to the AND and OR gate, the synthesis methods have been based on the "unate paradigm".To overcome the disadvantages of the current logic synthesis tools with respect to (nearly) linear functions and FPGA synthesis, this dissertation introduces an extended 3 theory of spectral methods for multiple-valued input, incompletely specified binary output logic. The spectral methods have not been popular in logic synthesis because of their four major drawbacks:(1) the computational complexity, especially if no Fast Transform exists, (2) the memory requirement to store the function in the necessary minterm representation, (3) they can not take efficiently advantage of incompletely specified functions, (4) suitable only for few applications in logic synthesis.To overcome the two last stated drawbacks, this dissertation introduces the T spectrum. The T spectrum separates the information obtained for the specified and not specified parts of the underlying function. Thus, it is possible to determine directly the contribution of the sp...

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“…The inverse transform is given by [12,27,71,73,74,90,92,[94][95][96][97]. In a disjoint representation of an mv function every minterm is covered only once.…”

Section: ::{)mentioning

confidence: 99%

Section: Iv2 Relations Of Specfral Techniques To Classical Logicmentioning

confidence: 99%

mentioning

confidence: 99%

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Orthogonal and Nonorthogonal Expansions for Multi-Level Logic Synthesis for Nearly Linear Functions and their Application to Field Programmable Gate Array Mapping

Schäfer¹

2000

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“…A Binary Decision Diagram (BDD) [2], [3], [5], [10], [18], [19], [21], [23], [24] is a Rooted Directed Acyclic Graph representation with Node (or Vertex) Set V and Edge Set E. The Node Set consists of two types of nodes: the nonterminal and terminal nodes. A nonterminal node v ∈ V has as attributes an index, denoted by index(v), to identify an input variable of a function, and two children (or successors), low(v) and high(v) ∈ V. A terminal node u ∈ V has no child, and it has a value, denoted by value(u).…”

Section: Basic Definitions and Propertiesmentioning

confidence: 99%

“…1 can be modified to cater for the synthesis of sequential circuits [17]. The recent article [6] caused even more interest in the Walsh spectrum by showing an efficient method of calculating this spectrum directly from its recursive definition rather than from the properties of the transform itself, as the earlier method [23], [24]. In the method [6], both the original data and resulting spectrum are stored in the form of Decision Diagrams.…”

Section: Introductionmentioning

confidence: 99%

Forward and inverse transformations between Haar spectra and ordered binary decision diagrams of Boolean functions

Falkowski

Chang

1997

IEEE Trans. Comput.

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Abstract-Unnormalized Haar spectra and Ordered Binary Decision Diagrams (OBDDs) are two standard representations of Boolean functions used in logic design. In this article, mutual relationships between those two representations have been derived. The method of calculating the Haar spectrum from OBDD has been presented. The decomposition of the Haar spectrum, in terms of the cofactors of Boolean functions, has been introduced. Based on the above decomposition, another method to synthesize OBDD directly from the Haar spectrum has been presented.

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Synthesis of multilevel multiplexer circuits for incompletely specified multioutput Boolean functions with mapping to multiplexer based FPGA's

Schäfer

Perkowski

1993

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Computation of Walsh spectrum from binary decision diagram and binary decision diagram from Walsh spectrum

Cited by 5 publications

References 11 publications

Orthogonal and Nonorthogonal Expansions for Multi-Level Logic Synthesis for Nearly Linear Functions and their Application to Field Programmable Gate Array Mapping

Orthogonal and Nonorthogonal Expansions for Multi-Level Logic Synthesis for Nearly Linear Functions and their Application to Field Programmable Gate Array Mapping

Forward and inverse transformations between Haar spectra and ordered binary decision diagrams of Boolean functions

Synthesis of multilevel multiplexer circuits for incompletely specified multioutput Boolean functions with mapping to multiplexer based FPGA's

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