Computation complexity analysis and VLSI architectures of shape coding for MPEG-4

Gong, Danian; He, Yun

doi:10.1117/12.386564

Cited by 6 publications

(6 citation statements)

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“…On the one hand, it is shown in [3] that shape encoding for test sequence weather with 10 frames per second (fps) QCIF (176 144) format requires 201.87 MIPS on an Ultra Sparc 2 workstation. On the other hand, [4] showed that CAE ranks the second place in and takes 19.61% of the total computation complexity of shape encoding in a typical case of MPEG-4 application, i.e., 30 fps CIF (352 288) video sequences. Thus, we can roughly estimate that CAE for test sequence weather with 10 fps QCIF would require 39.59 MIPS on an Ultra Sparc 2 workstation.…”

Section: Introductionmentioning

confidence: 97%

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A multisymbol context-based arithmetic coding architecture for MPEG-4 shape coding

Lee

Lin

Jen

2005

IEEE Trans. Circuits Syst. Video Technol.

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MPEG-4 shape coding comprises context-based arithmetic encoding (CAE) as its centerpiece. Since the CAE algorithm has a complicated coding procedure and strong data dependency, it is hard to exploit its pipeline and parallel facilities. Furthermore, to encode multiple symbols within one clock cycle, it needs to overcome the issues of extracting multiple contexts of these symbols, deriving multiple probabilities from these contexts, and performing multiple multiplicative range update operations. This paper presents an efficient pipelined multisymbol CAE architecture for real-time MPEG-4 shape encoding. The proposed design is based on the inherent characteristics of binary alpha blocks as well as the numerical properties of the probabilities indexed by the contexts, and it is capable of encoding either a singe symbol or multiple symbols within each clock cycle. To overcome the aforementioned issues under the consideration of the hardware cost and the critical path delay, only symbols with a particular set of contexts are chosen to be processed simultaneously within the same clock cycle. Theoretical analysis shows that the majority of symbols have contexts belonging to this particular set, and therefore CAE processing can be significantly accelerated. An example VLSI implementation of proposed architecture that encodes two symbols within each clock cycle without sacrificing the clock rate can achieve a speedup of 1.47 in comparison with traditional CAE architectures. This particular two-symbol design can support MPEG-4 Main Profile at levels 3 and 4 under extreme and typical conditions, respectively. When synthesized from Verilog RTL design by using TSMC 0.35-m 1P4M CMOS technology, the design can run at 90 MHz.Index Terms-Context-based arithmetic encoding, MPEG-4, shape coding.

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Section: Introductionmentioning

confidence: 97%

“…Dedicated shape coding hardware is also recommended for higher MPEG-4 profiles and levels due to its high computing property [3], [4]. On the one hand, it is shown in [3] that shape encoding for test sequence weather with 10 frames per second (fps) QCIF (176 144) format requires 201.87 MIPS on an Ultra Sparc 2 workstation.…”

Section: Introductionmentioning

confidence: 98%

A multisymbol context-based arithmetic coding architecture for MPEG-4 shape coding

Lee

Lin

Jen

2005

IEEE Trans. Circuits Syst. Video Technol.

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“…Several previous works [8], [11], [12] presented a few results on architecture design of MEPG-4 shape coding/decoding, but few of them reported a comprehensive design-space exploration and optimization. The contribution of this paper is the optimizations for the shape coding of MPEG-4 video coding derived at both the algorithm (bit-data parallelism) and architecture (parallel data flow optimization, data reuse) levels.…”

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confidence: 99%

VLSI architecture design of MPEG-4 shape coding

Chang¹,

Chang

Wang

et al. 2002

IEEE Trans. Circuits Syst. Video Technol.

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Abstract-This paper presents an efficient VLSI architecture design of MPEG-4 shape coding, which is the key technology for supporting the content-based functionality of the MPEG-4 Video standard. The real-time constraint of MPEG-4 shape coding leads to a heavy computational bottleneck on today's computer architectures. To overcome this problem, design analysis and optimization of MPEG-4 shape coding are addressed in this paper. By utilizing the RISC-based model, computational behaviors of the MPEG-4 shape coding tool are carefully examined and analyzed. The characteristic of a large amount of bit-level data processing and data transfer of MPEG-4 shape coding motivates us the optimization of bit-level data operations. Applying the data-flow optimization and data reuse techniques, bit-level computation-efficient architectures, such as data-dispatch-based binary-shaped motion estimation, the delay-line model, and configurable context-based arithmetic coding, are designed to accelerate bit-level processing. These hardware blocks are integrated and scheduled in a very efficient data flow to achieve real-time performance for MPEG-4 CPL2 specification at 23.5-MHz clock rate. The system architecture is implemented using Verilog HDL and synthesized with a 0.35-m four-layer CMOS standard library.

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“…Some works [3][4] have been presented on hardware designs of MPEG-4 shape encoder. In this work, we present a more efficient hardware design for the MPEG-4 shape encoder in terms of bandwidth and memory usage.…”

Section: Introductionmentioning

confidence: 99%

“…For example, the analysis of MPEG-4 Core Profile at Level 2 performed on a Ultra Sparc RISC indicated that MPEG-4 shape encoding requires giga scale operations and hundred mega byte scale memory access per second. To meet the stringent requirements on low cost and low power for the embedded system market, there is a clear need of the optimized VLSI architecture for MPEG-4 shape encoding.Some works [3][4] have been presented on hardware designs of MPEG-4 shape encoder. In this work, we present a more efficient hardware design for the MPEG-4 shape encoder in terms of bandwidth and memory usage.…”

mentioning

confidence: 99%

A bandwidth and memory efficient MPEG-4 shape encoder

Lee¹,

Chang²,

Chin³

et al.

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)

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-We have developed a shape encoder hardware for MPEG-4 video coding. On the one hand, the alpha component is compressed and therefore, the size and memory access of alpha frame memory can be reduced to 50% and 56.25% respectively. On the other hand, an efficient data transfer scheme combining the run length coding and addressing mode can reduce average data transfer time to 9.39% and accelerate the shape encoding process. The shape encoder can support MPEG-4 Main Profile at Level 4 in real-time. In addition, verification and testing methods are also considered. I. IntroductionMPEG-4's object-based scene description allows the transmission of arbitrarily shaped video objects [1][2]. The purpose of using shape is to promote a better subjective picture quality, a higher coding efficiency as well as more user interaction. These advantages make this standard best suited for the needs of mobile applications or browsing multimedia databases on the Internet. Therefore shape coding can be utilized in lots of consumer electronics devices, such as video telephony, PDA, and video surveillance. However, these flexible and high-efficient coding features are based on the complex decision process and high computational tasks that demand the high computing and high data traffic properties. For example, the analysis of MPEG-4 Core Profile at Level 2 performed on a Ultra Sparc RISC indicated that MPEG-4 shape encoding requires giga scale operations and hundred mega byte scale memory access per second. To meet the stringent requirements on low cost and low power for the embedded system market, there is a clear need of the optimized VLSI architecture for MPEG-4 shape encoding.Some works [3][4] have been presented on hardware designs of MPEG-4 shape encoder. In this work, we present a more efficient hardware design for the MPEG-4 shape encoder in terms of bandwidth and memory usage. In addition, the proposed design can also support higher level of MPEG-4 standard. We have successfully implemented the hardware shape encoder and ported the design on the ARM-based platform. The chip is fabricated using UMC 0.18µm CMOS 1P6M process. The design can support MPEG-4 Main Profile at Level 4, i.e., 489,600MB/sec with a frame size of 1920×1088.

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Computation complexity analysis and VLSI architectures of shape coding for MPEG-4

Cited by 6 publications

References 0 publications

A multisymbol context-based arithmetic coding architecture for MPEG-4 shape coding

A multisymbol context-based arithmetic coding architecture for MPEG-4 shape coding

VLSI architecture design of MPEG-4 shape coding

A bandwidth and memory efficient MPEG-4 shape encoder

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