Comprehensive study of variability in poly-Si channel nanowire transistor

Abstract

Variability in poly-Si nanowire transistors (NW Tr.) is studied with respect to device and grain size. Threshold voltage (Vth) variability decreases as grain size or NW width (W) decreases since the number of grain boundaries in carrier passage increases. Drain current (Id) variability shows similar grain size and W dependences, while Id variability in short channel Tr. is suppressed due to the parasitic resistance. In addition, Id variability decreases with high lateral or perpendicular electric field as well as high temperature due to potential barrier lowering at grain boundaries.