Comprehensive Assessment of Avalanche Operating Boundary of SiC Planar/Trench MOSFET in Cryogenic Applications

Qi, Jinwei; Yang, Xu; Li, Xin; Chen, Wenjie; Li, Teng; Tian, Kai; Huang, Xiaodong; Wang, Xuhui

doi:10.1109/tpel.2020.3034902

Cited by 20 publications

(9 citation statements)

References 28 publications

(25 reference statements)

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“…Figure 5b benchmarks the E AVA density of our HJD with homojunction-based Si, SiC, and GaN devices with a similar BV AVA . The E AVA density of our HJD is significantly higher than that of Si devices and comparable to the highest values reported in SiC and GaN devices 12 , 27 , 28 , 56 – 62 , In addition, as shown in Fig. 5c , our HJD shows an excellent combination of high surge current and surge energy comparable to the highest values reported in Si, SiC, and GaN devices 12 , 39 , 60 , 61 , 63 – 67 , Finally, as shown in Fig.…”

Section: Discussionsupporting

confidence: 82%

An avalanche-and-surge robust ultrawide-bandgap heterojunction for power electronics

et al. 2023

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Avalanche and surge robustness involve fundamental carrier dynamics under high electric field and current density. They are also prerequisites of any power device to survive common overvoltage and overcurrent stresses in power electronics applications such as electric vehicles, electricity grids, and renewable energy processing. Despite tremendous efforts to develop the next-generation power devices using emerging ultra-wide bandgap semiconductors, the lack of effective bipolar doping has been a daunting obstacle for achieving the necessary robustness in these devices. Here we report avalanche and surge robustness in a heterojunction formed between the ultra-wide bandgap n-type gallium oxide and the wide-bandgap p-type nickel oxide. Under 1500 V reverse bias, impact ionization initiates in gallium oxide, and the staggered band alignment favors efficient hole removal, enabling a high avalanche current over 50 A. Under forward bias, bipolar conductivity modulation enables the junction to survive over 50 A surge current. Moreover, the asymmetric carrier lifetime makes the high-level carrier injection dominant in nickel oxide, enabling a fast reverse recovery within 15 ns. This heterojunction breaks the fundamental trade-off between robustness and switching speed in conventional homojunctions and removes a key hurdle to advance ultra-wide bandgap semiconductor devices for power industrial applications.

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Section: Discussionsupporting

confidence: 82%

An avalanche-and-surge robust ultrawide-bandgap heterojunction for power electronics

et al. 2023

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“…where I peak is the peak value of i d , Q rr is the reverse recovery charge of the body diode, and S is the snappiness factor of the body diode. In the turn-off transient, the parasitic inductance in the loop will cause an obvious overshoot in u ds (Wu et al, 2020;Zhao et al, 2020a;Qi et al, 2021), and it has…”

Section: Switching Behaviorsmentioning

confidence: 99%

Influence of driving and parasitic parameters on the switching behaviors of the SiC MOSFET

Zhang

2023

Front. Energy Res.

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The SiC MOSFET has lower conduction loss and switching loss than the Si IGBT, which helps to improve the efficiency and power density of the converter, especially for those having strict requirements for volume and weight, for example, electrical vehicles (EVs), on-board chargers (OBCs), and traction drive systems (TDS). However, the faster switching speed will cause overshoot and oscillation problems, which will affect the efficiency and security of the SiC devices and power electronic systems. For the SiC MOSFET to be better used, combining a theoretical analysis, the double-pulse test platform is built. The controllable principles of SiC MOSFETs are validated. The turn-on and turn-off delay, switching delay, switching di/dt, switching du/dt, switching overshoot, and switching loss of SiC MOSFETs under different driving and parasitic parameters are explored. Finally, some valuable suggestions for designing are proposed for a better application of the SiC MOSFET.

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“…Typical Planar, Symmetrical and Asymmetrical trench MOSFETs models are referred to [8], [28], [29]. Key parameters have been listed in Table I.…”

Section: A Tcad Modelingmentioning

confidence: 99%

Degradation Analysis of Planar, Symmetrical and Asymmetrical Trench SiC MOSFETs Under Repetitive Short Circuit Impulses

Jahdi

Mellor

et al. 2023

IEEE Trans. Power Electron.

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In this paper, the reliability of Planar, Symmetrical, and Asymmetrical trench SiC MOSFETs is analysed under repetitive short circuit impulses at 300 K and 450 K. Both static and dynamic parameters are measured to characterize the degradation pattern of the three MOSFET structures. The degradation mechanisms are analysed and the internal electro-thermal behavior of MOSFETs is revealed through TCAD models. It has been found out that there is minor degradation for Planar SiC devices under both test conditions. The Symmetrical trench SiC MOSFET has the lowest reliability, which fails after 200 and 80 cycles at room and elevated temperature. The Asymmetrical trench SiC MOSFET has slightly higher reliability, failing after 1500 cycles and 500 cycles at room and elevated temperature, respectively. A comprehensive range of measurements until failure and the corresponding Silvaco TCAD analysis confirms that for both trench SiC MOSFETs, the deterioration of the gate oxide is responsible for the degradations and device failure. The higher the temperature, the higher electro-thermo-mechanical stress the devices suffer.

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Comprehensive Assessment of Avalanche Operating Boundary of SiC Planar/Trench MOSFET in Cryogenic Applications

Cited by 20 publications

References 28 publications

An avalanche-and-surge robust ultrawide-bandgap heterojunction for power electronics

An avalanche-and-surge robust ultrawide-bandgap heterojunction for power electronics

Influence of driving and parasitic parameters on the switching behaviors of the SiC MOSFET

Degradation Analysis of Planar, Symmetrical and Asymmetrical Trench SiC MOSFETs Under Repetitive Short Circuit Impulses

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