Compositional Reasoning

Giannakopoulou, Dimitra; Namjoshi, Kedar S.; Păsăreanu, Corina S.

doi:10.1007/978-3-319-10575-8_12

Cited by 20 publications

(9 citation statements)

References 55 publications

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“…A major breakthrough was made in 1990 with a series of papers by Graf [21] or they are merely cited without any further comment on the significance of their contributions [34]. These are injustices the present article tries to remedy.…”

Section: Resultsmentioning

confidence: 99%

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Compositional Verification in Action

Garavel

Lang

Mounier

2018

Formal Methods for Industrial Critical Systems

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Concurrent systems are intrinsically complex and their verification is hampered by the well-known "state-space explosion" issue. Compositional verification is a powerful approach, based on the divide-and-conquer paradigm, to address this issue. Despite impressive results, this approach is not used widely enough in practice, probably because it exists under multiple variants that make knowledge of the field hard to attain. In this article, we highlight the seminal results of Graf & Steffen and propose a survey of compositional verification techniques that exploit (or not) these results.

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Section: Resultsmentioning

confidence: 99%

“…There exist indeed alternative approaches, referred to as compositional reasoning, assume-guarantee, or rely-guarantee, which are often state-based and rely on model-checking concepts, including assertions, logic formulas and satisfaction relations. See, e.g., [66] and [34] for detailed presentations of these approaches.…”

Section: Introductionmentioning

confidence: 99%

Compositional Verification in Action

Garavel

Lang

Mounier

2018

Formal Methods for Industrial Critical Systems

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“…Among techniques to improve scalability are abstraction [18] and compositional reasoning (cf. [19]). The former removes details of the design, gaining scalability at the cost of possible false errors.…”

Section: Related Workmentioning

confidence: 99%

Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition

Chattopadhyay,

Lonsing,

Piccolboni

et al. 2021

Preprint

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Hardware accelerators (HAs) are essential building blocks for fast and energy-efficient computing systems. Accelerator Quick Error Detection (A-QED) is a recent formal technique which uses Bounded Model Checking for pre-silicon verification of HAs. A-QED checks an HA for self-consistency, i.e., whether identical inputs within a sequence of operations always produce the same output. Under modest assumptions, A-QED is both sound and complete. However, as is well-known, large design sizes significantly limit the scalability of formal verification, including A-QED. We overcome this scalability challenge through a new decomposition technique for A-QED, called A-QED with Decomposition (A-QED 2 ). A-QED 2 systematically decomposes an HA into smaller, functional sub-modules, called sub-accelerators, which are then verified independently using A-QED. We prove completeness of A-QED 2 ; in particular, if the full HA under verification contains a bug, then A-QED 2 ensures detection of that bug during A-QED verification of the corresponding subaccelerators. Results on over 100 (buggy) versions of a wide variety of HAs with millions of logic gates demonstrate the effectiveness and practicality of A-QED 2 . This article will appear in the proceedings of Formal Methods in Computer-Aided Design (FMCAD 2021).

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“…One path forward is to break a network up into smaller components and to tackle verification of each component in isolation. This approach has proven successful in the context of software verification [6,19,22,27,29] and in network data plane verification [30]. In such a modular verification system, one might declare an interface for each component that describes the set of routing messages the component can generate in a stable state.…”

Section: Introductionmentioning

confidence: 99%

Modular Control Plane Verification via Temporal Invariants

Alberdingk¹,

Beckett²,

Gupta³

et al. 2022

Preprint

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Satisfiability Modulo Theory (SMT)-based tools for network control plane analysis make it possible to reason exhaustively about interactions with peer networks and to detect vulnerabilities such as accidental use of a network as transit or prefix hijacking. SMT-based reasoning also facilitates synthesis and repair. To scale SMT-based verification to large networks, we introduce TIMEPIECE, a new modular control plane verification system. While past verifiers like Minesweeper [8] were based on analysis of stable paths, we show that such models, when deployed naïvely in service of modular verification, are unsound. To rectify the situation, we adopt a routing model based around a logical notion of time and develop a sound, expressive, and scalable verification engine.Our system requires that a user specifies interfaces between module components. We develop methods for defining these interfaces using predicates inspired by temporal logic, and show how to use those interfaces to verify a range of networkwide properties such as reachability, "no transit," and "no hijacking." Verifying a prefix-filtering policy using a nonmodular verification engine times out on a 320-node fattree network after 4 hours. However, TIMEPIECE verifies a 4,500node fattree in 6.5 minutes on a 96-core virtual machine. Modular verification of individual routers is embarrassingly parallel and completes in seconds, which allows verification to scale beyond non-modular engines, while still allowing the full power of SMT-based symbolic reasoning.

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Compositional Reasoning

Cited by 20 publications

References 55 publications

Compositional Verification in Action

Compositional Verification in Action

Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition

Modular Control Plane Verification via Temporal Invariants

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