Composable Flexible Real-time Packet Scheduling for Networks on-Chip

Abstract

Abstract-Network on chip is an emerging interconnection paradigm to address the scalability of traditional bus architecture. Time-critical systems need the capability to control packet delays in a network on-chip. The inflexibility and/or non-composability reduce the scalability of several proposed real-time service approaches for hard real-time networks onchip.In the era of "dark silicon" when large portions of multicore chips are turned off to save energy and control temperature, the incremental deployment capability of applications is crucial. In incremental deployment, application components are turned on and off. For time-critical applications, these components need to be composable in the sense that new incoming applications should not affect the behaviors of existing applications.In this paper, we propose a composable and flexible work-conserving packet scheduling discipline for hard real-time networks on chip. Our scheduling discipline employs an earliest deadline first (EDF) scheduler, which reduces average packet delays by 80% in comparison with a previous non-work-conserving EDF scheduling discipline running on the same 8×8 network with various popular traffic patterns. Our proposed scheduling discipline provides guaranteed service without sacrificing high consistent average performance. We also derive sufficient buffer sizes for our scheduling discipline. However, our scheduling discipline incurs a reasonable communication overhead.

Probabilistically time-analyzable complex processor designs

“…Literature on Networks-on-Chip (NoCs) for safety-related systems is abundant and includes buses, rings, trees and meshes among others [Jalle et al (2014), Panic et al (2013), Schoeberl et al (2012)]. Some designs are specifically tied to TDMA arbitration, such as Nostrum [Millberg et al (2004)] and Aethereal [Goossens et al (2005)], and require software layers to schedule at very fine granularity communications due to the use of contention-free packet transmissions [Bui & Lee (2012)]. This is generally unaffordable when cache memories are used for 6.6 Conclusions performance purposes due to the difficulties to schedule, for instance, cache misses.…”