Composability and Predictability for Independent Application Development,Verification, and Execution

Åkesson, Benny; Molnos, Anca; Hansson, Andreas; Angelo, Jude Ambrose; Goossens, Kees

doi:10.1007/978-1-4419-6460-1_2

Cited by 51 publications

(59 citation statements)

References 35 publications

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“…Whereas, the worst-case response time of a message depends on the length and available bandwidth of the route through the NoC. For being able to determine them during design time, two concepts are necessary [2]: predictability and composability. Predictability means that it is possible to give an upper bound of the worst-case response times of actor executions and message transmissions that are guaranteed to not being exceeded.…”

Section: Analyzing Stream Processing Applications On Invasive Mpsocsmentioning

confidence: 99%

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Invasive computing for timing-predictable stream processing on MPSoCs

Wildermann

Bäder

Bauer

et al. 2016

It - Information Technology

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Multi-Processor Systems-on-a-Chip (MPSoCs) provide sufficient computing power for many applications in scientific as well as embedded applications. Unfortunately, when real-time requirements need to be guaranteed, applications suffer from the interference with other applications, uncertainty of dynamic workload and state of the hardware. Composable application/architecture design and timing analysis is therefore a must for guaranteeing real-time applications to satisfy their timing requirements independent from dynamic workload. Here, Invasive Computing is used as the key enabler for compositional timing analysis on MPSoCs, as it provides the required isolation of resources allocated to each application. On the basis of this paradigm, this work proposes a hybrid application mapping methodology that combines designtime analysis of application mappings with run-time management. Design space exploration delivers several resource reservation configurations with verified real-time guarantees for individual applications. These timing properties can then be guaranteed at run-time, as long as dynamic resource allocations comply with the offline analyzed resource configurations. This article describes our methodology and presents programming, optimization, analysis, and hardware techniques for enforcing timing predictability. A case study illustrates the timing-predictable management of real-time computer vision applications in dynamic robot system scenarios.

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Section: Analyzing Stream Processing Applications On Invasive Mpsocsmentioning

confidence: 99%

“…As a remedy, the concept of composability has become prominent [2]. A composable design allows to analyze the execution properties of one application already at design time without knowing the other applications.…”

Section: Introductionmentioning

confidence: 99%

Invasive computing for timing-predictable stream processing on MPSoCs

Wildermann

Bäder

Bauer

et al. 2016

It - Information Technology

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“…We filter out the L2 cache misses and obtain the transactions to the DRAM memory. We then employ a trace player to simulate the application behavior in a SystemC simulation model of the CompSOC platform [18]. We forward these transactions from the trace player to a DRAM memory controller [17] in platform, which is modified to employ our predictor and the power saving policy logic.…”

Section: A Experimental Setupmentioning

confidence: 99%

A Predictor-Based Power-Saving Policy for DRAM Memories

Thomas

Chandrasekar

Åkesson

et al. 2012

2012 15th Euromicro Conference on Digital System Design

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Abstract-Reducing power/energy consumption is an important goal for all computer systems, from servers to battery-driven hand-held devices. To achieve this goal, the energy consumption of all system components needs to be reduced. One of the most power-hungry components is the off-chip DRAM, even when it is idle. DRAMs support different power-saving modes, such as self-refresh and power-down, but employing them every time the DRAM is idle, reduces performance due to their power-up latencies. The self-refresh mode offers large power savings, but incurs a long power-up latency. The power-down mode, on the other hand, has a shorter power-up latency, but provides lower power savings.In this paper, we propose and evaluate a novel power-saving policy that combines the best of both power-saving modes in order to achieve significant power reductions with a marginal performance penalty. To accomplish this, we use a history-based predictor to forecast the duration of an idle period and then either employ self-refresh, or power-down, or a combination of both power saving modes. Significant refinements are made to the predictor to maximize the energy savings and minimize the performance penalty. The presented policy is evaluated using several applications from the multimedia domain and the experimental results show that it reduces the total DRAM energy consumption between 68.8% and 79.9% at a negligible performance penalty between 0.3% and 2.2%.

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“…We address the verification problem using two complexityreducing concepts: predictability and composability [9]. Predictable systems bound interference between applications.…”

Section: Introductionmentioning

confidence: 99%

“…This means that the interference experienced by an application is independent of others. Note that with these definitions predictability does not imply composability or the other way around [9]. Composable systems address the verification problem in the following four ways [10]: 1) Applications can be verified in isolation, resulting in a linear and non-circular verification process [7].…”

Section: Introductionmentioning

confidence: 99%

Architectures and modeling of predictable memory controllers for improved system integration

Åkesson

Goossens

2011

2011 Design, Automation &Amp; Test in Europe

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Abstract-Designing multi-processor systems-on-chips becomes increasingly complex, as more applications with realtime requirements execute in parallel. System resources, such as memories, are shared between applications to reduce cost, causing their timing behavior to become inter-dependent. Using conventional simulation-based verification, this requires all concurrently executing applications to be verified together, resulting in a rapidly increasing verification complexity. Predictable and composable systems have been proposed to address this problem. Predictable systems provide bounds on performance, enabling formal analysis to be used as an alternative to simulation. Composable systems isolate applications, enabling them to be verified independently.Predictable and composable systems are built from predictable and composable resources. This paper presents three general techniques to implement and model predictable and composable resources, and demonstrates their applicability in the context of a memory controller. The architecture of the memory controller is general and supports both SRAM and DDR2/DDR3 SDRAM and a wide range of arbiters, making it suitable for many predictable and composable systems. The modeling approach is based on a shared-resource abstraction that covers any combination of supported memory and arbiter and enables system-level performance analysis with a variety of well-known frameworks, such as network calculus or data-flow analysis.

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Composability and Predictability for Independent Application Development,Verification, and Execution

Cited by 51 publications

References 35 publications

Invasive computing for timing-predictable stream processing on MPSoCs

Invasive computing for timing-predictable stream processing on MPSoCs

A Predictor-Based Power-Saving Policy for DRAM Memories

Architectures and modeling of predictable memory controllers for improved system integration

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