Complexity Study of the Continuous Valued Number System Adders

Zamanlooy, Babak; Novak, Ashley; Mirhassani, Mitra

doi:10.1109/ismvl.2012.36

Cited by 2 publications

(3 citation statements)

References 18 publications

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“…The CVNS adder can reduce the number of interconnections and achieve area and power savings [14]. In this section, the basic CVNS adder (ADD b ) [3], the Group adder (ADD g ) [8], and our new methods, truncation based on the uniform method (ADD tu ) and sliding method (ADD ts ), are compared.…”

Section: Processing Element Countmentioning

confidence: 99%

“…In this section, the basic CVNS adder (ADD b ) [3], the Group adder (ADD g ) [8], and our new methods, truncation based on the uniform method (ADD tu ) and sliding method (ADD ts ), are compared. Comparisons are also made between the system complexities in terms of number of required gates, fan-in and fan-out of the system, system resolution, and finally gate and system sizes [14].…”

Section: Processing Element Countmentioning

confidence: 99%

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Robust Analog Arithmetic Based on the Continuous Valued Number System

Zamanlooy

Mirhassani

2017

Embedded Systems Design With Special Arithmetic and Number Systems

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To implement arithmetic architectures there are many approaches available, some with new logic families such as Multiple-Valued-Logic (MVL) [1,2]. In this type of arithmetic systems, the signal levels in the digits are increased from a conventional two-state binary to multiple values. This feature is specially interesting for hardware implementation of neural networks, where a high number of interconnections are required between the network layers. Using a multiple-valued number system can reduce the number of interconnections, and hence reduce the area and power consumption of the circuit.The Continuous Valued Number System (CVNS) falls within the MVL arithmetic category. The CVNS and the basic concept of analog-digits were first introduced in [3], fundamental methods of addition arithmetic and array multiplication were developed in [4,5], and circuit design issues were discussed in [6] and [7].The radix-2 CVNS arithmetic has been very effective and used in development of a series of arithmetic units [8][9][10][11]. This class of the CVNS can interface with the digital inputs directly, and the conversion process between the two number systems is very simple. The radix-2 CVNS is also used for implementation of mixed-signal multipliers [12]. The multiplier is useful for implementation of high density CVNS neural networks, where a high number of adders and multipliers are required. The CVNS multiplier is compact, area efficient, and its operations are verified under different environmental conditions.

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Section: Processing Element Countmentioning

confidence: 99%

Section: Processing Element Countmentioning

confidence: 99%

Robust Analog Arithmetic Based on the Continuous Valued Number System

Zamanlooy

Mirhassani

2017

Embedded Systems Design With Special Arithmetic and Number Systems

View full text Add to dashboard Cite

show abstract

“…In the first one a ripple carry adder [8][9][10][11][12][13][14][15][16][17] was used while in the second one a pre-fix tree of sklansky type adder [18][19][20][21][22][23][24][25] was used. The adder is a very important component in digital systems, so lot of research has been done in past on various types of adders to improve the speed and area requirements [26][27][28][29][30][31][32][33][34][35][36][37][38][39][40][41]. Apart from adder both the ALUs consisted of a Logical and Shifter blocks.…”

Section: Introductionmentioning

confidence: 99%

Comparative Analysis of ALU Implementation with RCA and Sklansky Adders In ASIC Design Flow

Buzdar¹,

Sun²,

Buzdar³

2016

ijacsa

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Abstract-An Arithmetic Logic Unit (ALU) is the heart of every central processing unit (CPU) which performs basic operations like addition, subtraction, multiplication, division and bitwise logic operations on binary numbers. This paper deals with implementation of a basic ALU unit using two different types of adder circuits, a ripple carry adder and a sklansky type adder. The ALU is designed using application specific integrated circuit (ASIC) platform where VHDL hardware description language and standard cells are used. The target process technology is 130nm CMOS from the foundry ST Microelectronics. The Cadence EDA tools are used for the ASIC implementation. A comparative analysis is provided for the two ALU circuits designed in terms of area, power and timing requirements.

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Complexity Study of the Continuous Valued Number System Adders

Cited by 2 publications

References 18 publications

Robust Analog Arithmetic Based on the Continuous Valued Number System

Robust Analog Arithmetic Based on the Continuous Valued Number System

Comparative Analysis of ALU Implementation with RCA and Sklansky Adders In ASIC Design Flow

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