Complexity evaluation of non-binary Galois field LDPC code decoders

Lehnigk-Emden, Timo; Wehn, Norbert

doi:10.1109/istc.2010.5613874

Cited by 19 publications

(15 citation statements)

References 15 publications

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“…In the layered decoding approach [29]- [31], the parity check matrix is partitioned into layers (12) Accordingly, each layer associates with one super-code , and the original code can be treated as the intersection of all super-codes (13) The column weight of each layer is restricted to be equal or less than 1.…”

Section: A Review Of Layered Decoding Algorithmmentioning

confidence: 99%

A Network-Efficient Nonbinary QC-LDPC Decoder Architecture

Zhang

Parhi

2012

IEEE Trans. Circuits Syst. I

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Nonbinary low-density parity-check (LDPC) codes are of great interest due to their better performance cover binary ones when the code length is moderate. However, the cost of decoder implementation for these LDPC codes is still very high. In this paper, a low-complexity VLSI architecture for nonbinary LDPC decoders is presented. By exploiting the intrinsic shifting and symmetry properties of nonbinary quasi-cyclic LDPC (QC-LDPC) codes, significant reduction of memory size and routing complexity can be achieved. These unique features lead to two network-efficient decoder architectures for Class-I and Class-II nonbinary QC-LDPC codes, respectively. Comparison results with the state-of-the-art designs show that for the code example of the 64-ary (1260, 630) rate-0.5 Class-I code, the proposed scheme can save up to 70.6% hardware required by switch network, which demonstrates the efficiency of the proposed technique. The proposed design for the 32-ary (992, 496) rate-0.5 Class-II code can achieve a 93.8% switch network complexity reduction compared with conventional approaches. Furthermore, with the help of a generator for possible solution sequences, both forward and backward steps can be eliminated to offer processing convenience of check node unit (CNU) blocks. Results show the proposed 32-ary (992, 496) rate-0.5 Class-II decoder can achieve 4.47 Mb/s decoding throughput at a clock speed of 150 MHz.

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Section: A Review Of Layered Decoding Algorithmmentioning

confidence: 99%

A Network-Efficient Nonbinary QC-LDPC Decoder Architecture

Zhang

Parhi

2012

IEEE Trans. Circuits Syst. I

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“…Our design is also more efficient than the one in [9]. In [10] and [11], the field-programmable gate array (FPGA)-based results cannot be compared directly. However, considering the efficiency of the path construction method, the new architecture should cost less hardware.…”

Section: B Comparison With Other Implementation Schemesmentioning

confidence: 99%

Nonbinary LDPC Code Decoder Architecture With Efficient Check Node Processing

Sha

Wang

2012

IEEE Trans. Circuits Syst. II

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Nonbinary low-density parity-check (NB-LDPC) codes are an extension of binary LDPC codes with significantly better performance. Although various kinds of low-complexity iterative decoding algorithms have been proposed, the VLSI implementation of NB-LDPC decoders still remains a big challenge due to its high complexity and long latency. In this brief, a highly efficient check node processing scheme, which the processing delay greatly reduced, is proposed for Min-max decoding algorithm. Thereafter, an efficient check node unit (CNU) can be designed. Compared with previous works, the latency of the CNU could be reduced to less than 52%. In addition, a decoder for a (620, 310) NB-LDPC code is designed to demonstrate the efficiency of the presented techniques.Index Terms-Low-density parity-check (LDPC) codes, min-max decoding, nonbinary, VLSI design.

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“…Several studies were performed on the decoding algorithms for NB-LDPC codes. Although belief propagation [1] and the Fourier domain decoding algorithm [2] show high error-correction performances, their decoding complexities are significantly high. Symbol-flipping algorithms offer low decoding complexity but significantly degraded errorcorrection performance [3,4].…”

Section: Introductionmentioning

confidence: 99%

Selection-based Low-cost Check Node Operation for Extended Min-Sum Algorithm

Park

Chung²

2021

KSII TIIS

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Although non-binary low-density parity-check (NB-LDPC) codes have better error-correction capability than that of binary LDPC codes, their decoding complexity is significantly higher. Therefore, it is crucial to reduce the decoding complexity of NB-LDPC while maintaining their error-correction capability to adopt them for various applications. The extended min-sum (EMS) algorithm is widely used for decoding NB-LDPC codes, and it reduces the complexity of check node (CN) operations via message truncation. Herein, we propose a low-cost CN processing method to reduce the complexity of CN operations, which take most of the decoding time. Unlike existing studies on low complexity CN operations, the proposed method employs quick selection algorithm, thereby reducing the hardware complexity and CN operation time. The experimental results show that the proposed selection-based CN operation is more than three times faster and achieves better error-correction performance than the conventional EMS algorithm.

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Complexity evaluation of non-binary Galois field LDPC code decoders

Cited by 19 publications

References 15 publications

A Network-Efficient Nonbinary QC-LDPC Decoder Architecture

A Network-Efficient Nonbinary QC-LDPC Decoder Architecture

Nonbinary LDPC Code Decoder Architecture With Efficient Check Node Processing

Selection-based Low-cost Check Node Operation for Extended Min-Sum Algorithm

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