Abstract:State of the art formal verification is based on formal methods and its goal
is proving given correctness properties. For example, a PSTM scheduler was
modeled in CSP in order to prove deadlock-freeness and starvation-freeness.
However, as this paper shows, using solely formal methods is not sufficient.
Therefore, in this paper we propose a complete formal verification of
trustworthy software, which jointly uses formal verification and formal
model testing. As an example, we first test the pr… Show more
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