2009
DOI: 10.1143/jjap.48.04c048
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Complementary Metal–Oxide–Silicon Field-Effect-Transistors Featuring Atomically Flat Gate Insulator Film/Silicon Interface

Abstract: In this paper, we demonstrate newly developed process technology to fabricate complementary metal-oxide-silicon field-effect transistors (CMOSFETs) having atomically flat gate insulator film/silicon interface on (100) orientated silicon surface. They include 1,200 C ultraclean argon ambient annealing technology for surface atomically flattening and radical oxidation technology for device isolation, flatness recovery after ion implantation, and gate insulator formation. The fabricated CMOSFET with atomically fl… Show more

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Cited by 41 publications
(52 citation statements)
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References 18 publications
(28 reference statements)
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“…With Si, several methods have been developed such as sacrificial oxidation, 5) wet chemical treatment, 6) argon or hydrogen (H 2 ) gas annealing. [7][8][9][10] Although it is well known that surface treatment in high vacuum is effective for obtaining an atomically flat surface on the Ge substrate, 11) no investigation of atomically flat Ge surfaces by using conventional process technology has been reported. Therefore, in this paper, we investigated the impact of sacrificial oxidation and H 2 annealing on the surface morphology of Ge.…”
mentioning
confidence: 99%
“…With Si, several methods have been developed such as sacrificial oxidation, 5) wet chemical treatment, 6) argon or hydrogen (H 2 ) gas annealing. [7][8][9][10] Although it is well known that surface treatment in high vacuum is effective for obtaining an atomically flat surface on the Ge substrate, 11) no investigation of atomically flat Ge surfaces by using conventional process technology has been reported. Therefore, in this paper, we investigated the impact of sacrificial oxidation and H 2 annealing on the surface morphology of Ge.…”
mentioning
confidence: 99%
“…[12][13][14] The Si surface thus had monoatomic steps with a height of 0.136 nm and atomically flat terraces with a width of approximately 150 nm. The surface roughness in each terrace was 0.03 nm; it was less than the detection limit of atomic force microscopy.…”
Section: Methodsmentioning
confidence: 99%
“…And a small trap density insulator film should be formed above the PD for suppressing the fixed charge generation due to trapping of the carriers excited by high photon energy UV-light. Here, the atomically flat Si surface is formed by annealing a bare Si surface wafer at around 800°C or above in an ultra-pure Ar ambient with a residue H 2 O concentration of 30 ppb or less [20,21,22]. By this process, a flat Si surface formed by atomic terrace and mono-atomic layer steps are obtained [20].…”
Section: Introductionmentioning
confidence: 99%
“…By this process, a flat Si surface formed by atomic terrace and mono-atomic layer steps are obtained [20]. In addition, by an alkali-free wet cleaning process in dark ambient condition for bare Si wafer to suppress the local Si etching and by an oxygen radical oxidation process with isotropic oxidation reaction, the atomic flatness level is maintained through the device fabrication process [20,21]. through 7 nm thick oxide film.…”
Section: Introductionmentioning
confidence: 99%