Complementary mask pattern split for 8 in. stencil masks in electron projection lithography

Yamashita, Hiroshi; Takahashi, Kimitoshi; Amemiya, Isao; Takeuchi, Kunio; Masaoka, Hideki; Takenaka, Hiroshi; Yamabe, Masaki

doi:10.1116/1.1518019

Cited by 13 publications

(9 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…8 We proved that the stencil mask for the corrected data by our PEC system could be reliably fabricated. complementary split Si stencil mask of two Anaheims processed by our PEC system was fabricated by HOYA ͑Fig.…”

Section: Resultsmentioning

confidence: 66%

See 1 more Smart Citation

High-performance proximity effect correction for sub-70 nm design rule system on chip devices in 100 kV electron projection lithography

Ogino

Hoshino

Machida

et al. 2003

Journal of Vacuum Science &Amp; Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena

Self Cite

View full text Add to dashboard Cite

Articles you may be interested inElectron-beam direct writing system employing character projection exposure with production dispatching rule Performances by the electron optical system of low energy electron beam proximity projection lithography tool with a large scanning field Approach to full-chip simulation and correction of stencil mask distortion for proximity electron lithography Proximity effect correction using pattern shape modification and area density map for electron-beam projection lithography J.The proximity effect correction ͑PEC͒ system to achieve the practical processing time and data volume for sub-65 nm design-rule system on chip ͑SoC͒ devices is improved. The lump method, which is the technique to process several subfields at a time, is used to reduce the processing time for PEC. The hierarchical data processing for PEC is also proposed to reduce the data volume. A PC cluster system has been used to reduce the processing time for PEC. For an actual 70 nm design-rule SoC device data, the processing time has been reduced from 7.8 h to 10.3 min and the data volume has been reduced from 12.4 to 2.6 GB by using the lump method, the hierarchical data processing, and a ten PC cluster system. And, we have confirmed that the required critical dimension accuracy of Ϯ5% is achieved for the device data in the simulation. We have successfully fabricated a full-size 8 in. Si stencil mask using the data with our PEC system for an actual 70 nm design-rule SoC device.

show abstract

Section: Resultsmentioning

confidence: 66%

“…8 The original layout data is split into 250-m-square subfields ͑SFs͒ on the wafer by the subfield split. It is also effective for logic devices to rehierarchicalize the flattened data by extracting polygons that have identical shapes as a cell.…”

Section: B Hierarchical Proximity Effect Correctionmentioning

confidence: 99%

High-performance proximity effect correction for sub-70 nm design rule system on chip devices in 100 kV electron projection lithography

Ogino

Hoshino

Machida

et al. 2003

Journal of Vacuum Science &Amp; Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena

Self Cite

View full text Add to dashboard Cite

show abstract

“…The pattern data was Selete's actual 70-nm design-rule system on chip (SoC) device named Anaheim containing CPU, logic, DRAM and SRAM, and the data was divided into complementary pattern by the complementary mask pattern split program M-Split [10]. Fig.…”

Section: -Mm Mask Fabricationmentioning

confidence: 99%

200-mm EPL stencil mask fabrication by using SOI substrate

et al. 2003

View full text Add to dashboard Cite

We developed 200-mm stencil masks for electron projection lithography (EPL) by using silicon-on-insulator (SOI) substrates. Stress of a 2-µm-thick single crystalline silicon membrane, where patterns were fabricated as openings, was controlled around 10 MPa by adjusting concentration of impurities doped into the SOI layer. Boron and phosphorus were investigated as doping impurities, and it was confirmed that doping both elements were capable of stress control. For forming struts that supported the thin membrane, a time multiplexed etch method was applied. Control of the deep etch parameters made it possible for the SiO 2 stopper layer not to be etched through even if its thickness was sub-microns. To fabricate pattern openings in the membrane, reactive ion etching with high-density plasma was applied and lines down to 140 nm was fabricated in a 200-mm mask. Image placement distortion within a subfield was measured across the 200-mm mask and magnitudes of the image placement distortion were typically ~15 nm (3σ). A 200-mm EPL stencil mask having Selete's actual 70-nm design-rule system on chip (SoC) device pattern was successfully fabricated. We confirmed that the SOI substrates had potential abilities as initial material for 200-mm stencil mask fabrication.

show abstract

“…The feasibility of the parallel processing method has been already presented by Selete [2]. Since the EPL mask data is divided into subfields which are independent from each other, the idea of parallel processing method is suitable for the aim of the total time reduction.…”

Section: Problems 31 Computation Timementioning

confidence: 99%

EPL mask data conversion system EPLON

et al. 2003

View full text Add to dashboard Cite

EPLON is the name of a system that we have been developing as a data conversion system for EPL masks in order to meet the requirements of EPL stencil masks. In our paper we presented in PMJ2002, we proved that our system could convert the whole chip data. However we still had some problems to overcome, one of which is a problem of conversion time and another issue is a data volume problem.This paper presents the features of our multi process computation method and the data compaction with building a hierarchy from the flattened data.

show abstract

Complementary mask pattern split for 8 in. stencil masks in electron projection lithography

Cited by 13 publications

References 9 publications

High-performance proximity effect correction for sub-70 nm design rule system on chip devices in 100 kV electron projection lithography

High-performance proximity effect correction for sub-70 nm design rule system on chip devices in 100 kV electron projection lithography

200-mm EPL stencil mask fabrication by using SOI substrate

EPL mask data conversion system EPLON

Contact Info

Product

Resources

About