Complementary heterostructure FET technology for low power, high speed digital applications

Fulkerson, D.E.; Baier, S.M.; Nohava, J.C.; Hochhalter, Rod

doi:10.1016/0038-1101(95)00166-2

Cited by 15 publications

(9 citation statements)

References 12 publications

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“…The fabrication process has been described elsewhere [6]. A test chip consisting of individual transistors and test structures was submitted along with the serializer in order to be able to extract transistor parameters.…”

Section: Resultsmentioning

confidence: 99%

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A low-power, radiation-hard gigabit serializer for use in the CMS electromagnetic calorimeter

Denes

Baier²,

Bussat³

et al. 2000

IEEE Trans. Nucl. Sci.

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Abstract-An integrated fiber-optic bit serializer and VCSEL (Vertical Cavity Surface Emitting Laser) driver has been constructed in radiation-hard complementary heterostructure GaAs FET (CHFET) technology. The serializer, which converts 20 parallel inputs into a high-speed serial output, consumes 60 mW at nominal supply voltage when operating at the Large Hadron Collider (LHC) word rate of 40 MHz (0.8-GB/s serial rate). The integrated driver directly drives a VCSEL and provides 10-mA switched current and 5 mA of prebias. The complete digital optical link thus consumes 90 mW.

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Section: Resultsmentioning

confidence: 99%

“…The actual implementation of the logic described for makes use of feedback FET logic (FFL) [6]. An FFL inverter is shown in Fig.…”

Section: To Prevent Thismentioning

confidence: 99%

A low-power, radiation-hard gigabit serializer for use in the CMS electromagnetic calorimeter

Denes

Baier²,

Bussat³

et al. 2000

IEEE Trans. Nucl. Sci.

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“…Due to the proprietary nature of the complementary GaAs parameters, Table 1 lists the composite set of HSPICE (level 3, JFET) parameters based on a number of complementary GaAs processes, including Honeywell [4], Sandia [5], University of Lille [6] and MIT [7].…”

Section: Choice Of Gaas Technologymentioning

confidence: 99%

<title>Novel extension of neu-MOS techniques to neu-GaAs</title>

1999

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The neuron-MOS (neu-MOS) transistor, recently discovered by Shibata and Ohmi in 1991 [T. Shibata, T. Ohmi, International Electron Devices Meeting, Technical Digest, 1991] Microelectronics, vol. 1, 1995, pp. 11-18]. This paper extends the neu-MOS paradigm to complementary gallium arsenide based on HIGFET transistors. The design and HSPICE simulation results of a neu-GaAs ripple carry adder are presented, demonstrating the potential for very significant transistor count and area reduction through the use of neu-GaAs in VLSI design. Preliminary simulations indicate a reduction of a factor of four in transistor count for the same power dissipation as conventional complementary GaAs. The small gate leakage is shown to be useful in eliminating unwanted charge build-up on the floating gate. ᭧

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“…Furthermore, the co-integration of n-and p-channel HFETs has attracted considerable attention for extremely low power dissipation associated with complementary logic circuit applications [7][8][9]. In this article, the InGaP/InGaAs/GaAs integrated complementary DCFETs are well reported and demonstrated.…”

Section: Introductionmentioning

confidence: 99%