Compiling Ruby into FPGAs

Guo, Shaori; Luk, Wayne

doi:10.1007/3-540-60294-1_112

Cited by 17 publications

(5 citation statements)

References 7 publications

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“…The functional parts of these languages are often used for macro generation of the hardware netlists. Similar approaches are seen in other languages like muFP [21], Ruby [5] and Hawk [4].…”

Section: Related Workmentioning

confidence: 55%

Stream processing hardware from functional language specifications

Frankau

Mycroft

2003

36th Annual Hawaii International Conference on System Sciences, 2003. Proceedings of The

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We describe work-in-progress which aims at compiling suitably restricted functional programs with lazy lists directly into hardware. This extends previous work on SAFL which demonstrated that functional languages are effective at describing "fire-and-wait-for-result" programs, but for which stream-like I/O was awkward or impossible. Other frameworks (e.g. Lava) have used functional languages as a form of macro-language, so that executing a program generates a net-list (structural) description, while our language is compiled directly ("behaviourally") to hardware. In particular our stream operations (represented as creation and pattern matching of lazy CONS cells) are mapped into channel writes and reads. We introduce our language, SASL, compare our approach to that of synchronous stream/signal languages, and give example functional descriptions which can be compiled to hardware.

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“…The functional parts of these languages are often used for macro generation of the hardware netlists. Similar approaches are seen in other languages like muFP [21], Ruby [5] and Hawk [4].…”

Section: Related Workmentioning

confidence: 55%

Stream processing hardware from functional language specifications

Frankau

Mycroft

2003

36th Annual Hawaii International Conference on System Sciences, 2003. Proceedings of The

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“…· Develop the most ecient implementation of the repeating units before hardware compilation, using device-speci®c descriptions like OAL if necessary. The system has been used in developing a number of regular array designs, including a systolic convolver [11], a systolic priority queue [9], a systolic sorter [10], a sine calculator [8], and in developing recon®gurable libraries for FPGAs [24,25]. It has also been used in producing implementations partly in hardware and partly in software [23].…”

Section: Resultsmentioning

confidence: 99%

An integrated system for developing regular array designs

Guo¹,

Luk

2001

Journal of Systems Architecture

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This paper describes an integrated system for developing regular array designs based on the block description language Ruby. Ruby supports concise design description and formal veri®cation. A parametrised Ruby description can be used in simulating, re®ning and visualising designs, and in compiling hardware implementations such as ®eld programmable gate arrays. Our system enables rapid design production, while good design quality is achieved by (a) the ecient instantiation of device-speci®c libraries, (b) the size optimisation of bit-level components using the design re®ner, and (c) the exploitation of regularity information at source level in the library composition process. The development and implementation of several median ®lters are used to illustrate the system. Ó

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“…Using Ruby [18], we designed an OoO generator to generate Verilog-HDL codes with an arbitarary number for latency, dimension, and set. The OoO mechanisms used in the evaluation were generated automatically by this generator.…”

Section: Mechanismmentioning

confidence: 99%

Reconfigurable Out-of-Order System for Fluid Dynamics Computation Using Unstructured Mesh

Akamine

Talip

Osana

et al. 2014

IEICE Trans. Inf. & Syst.

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SUMMARYComputational fluid dynamics (CFD) is an important tool for designing aircraft components. FaSTAR (Fast Aerodynamics Routines) is one of the most recent CFD packages and has various subroutines. However, its irregular and complicated data structure makes it difficult to execute FaSTAR on parallel machines due to memory access problem. The use of a reconfigurable platform based on field programmable gate arrays (FPGAs) is a promising approach to accelerating memory-bottlenecked applications like FaSTAR. However, even with hardware execution, a large number of pipeline stalls can occur due to read-after-write (RAW) data hazards. Moreover, it is difficult to predict when such stalls will occur because of the unstructured mesh used in FaSTAR. To eliminate this problem, we developed an out-of-order mechanism for permuting the data order so as to prevent RAW hazards. It uses an execution monitor and a wait buffer. The former identifies the state of the computation units, and the latter temporarily stores data to be processed in the computation units. This out-of-order mechanism can be applied to various types of computations with data dependency by changing the number of execution monitors and wait buffers in accordance with the equations used in the target computation. An out-of-order system can be reconfigured by automatic changing of the parameters. Application of the proposed mechanism to five subroutines in FaSTAR showed that its use reduces the number of stalls to less than 1% compared to without the mechanism. In-order execution was speeded up 2.6-fold and software execution was speeded up 2.9-fold using an Intel Core 2 Duo processor with a reasonable amount of overhead. key words: computational fluid dynamics (CFD), field programmable gate array (FPGA), scientific computations, reconfigurable hardware, out-oforder system

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Compiling Ruby into FPGAs

Cited by 17 publications

References 7 publications

Stream processing hardware from functional language specifications

Stream processing hardware from functional language specifications

An integrated system for developing regular array designs

Reconfigurable Out-of-Order System for Fluid Dynamics Computation Using Unstructured Mesh

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