Compiling irregular applications for reconfigurable systems

Abstract

Algorithms that exhibit irregular memory access patterns are known to show poor performance on multiprocessor architectures, particularly when memory access latency is variable. Many common data structures, including graphs, trees, and linked-lists, exhibit these irregular memory access patterns. While FPGA-based code accelerators have been successful on applications with regular memory access patterns, they have not been further explored for irregular memory access patterns. Multithreading has been shown to be an effective technique in masking long latencies. We describe the compiler generation of concurrent hardware threads for FPGAs with the objective of masking the memory latency caused by irregular memory access patterns. The CHAT compiler extends the ROCCC toolset to generate customised state information for each dynamically generated thread. Initial results show a speed-up of 50x.

On the field design bug tolerance on a multi-core processor using FPGA

“…If for 1 million instructions, design bugs happen with the same proportion as that given in Figure 5 the results in Figure 6 are obtained. The performance of the proposed system can be further improved by following the technique specified in Halstead et al (2014) and Ouni and Mtibaa (2014) that deals with improving memory access for FPGA applications. Figure 6 can be extended to compare the existing degraded mode execution time and proposed recovery execution time for varying numbers of instructions as given in Figure 7.…”

FPGAs for Software Programmers

“…The Compiled Hardware Accelerated Threads (CHAT) tool is designed to assist developers with implementing irregular applications on FPGAs [HVN14]. CHAT is built using the ROCCC toolset.…”

“…CHAT is built using the ROCCC toolset. MT-FPGA (Multithreading on FPGAs) [HVN14] is an execution model that combines the memory masking ability of multithreaded execution with a customized data path. However, while the focus of ROCCC is on generating highly optimized kernels for streaming applications, the focus of CHAT is on kernels for irregular applications (Fig.…”

Compiled multithreaded data paths on FPGAs for dynamic workloads

“…The CHAT [18], [19] compiler uses the same underlying tools as ROCCC for Hi-CIRRF and Lo-CIRRF compilation, but it targets irregular applications. Initially, it focused on irregular kernels with a deterministic number of threads, and each thread has a deterministic workload.…”