Compiling for reconfigurable computing

Abstract

Reconfigurable computing platforms offer the promise of substantially accelerating computations through the concurrent nature of hardware structures and the ability of these architectures for hardware customization. Effectively programming such reconfigurable architectures, however, is an extremely cumbersome and error-prone process, as it requires programmers to assume the role of hardware designers while mastering hardware description languages, thus limiting the acceptance and dissemination of this promising technology. To address this problem, researchers have developed numerous approaches at both the programming languages as well as the compilation levels, to offer high-level programming abstractions that would allow programmers to easily map applications to reconfigurable architectures. This survey describes the major research efforts on compilation techniques for reconfigurable computing architectures. The survey focuses on efforts that map computations written in imperative programming languages to reconfigurable architectures and identifies the main compilation and synthesis techniques used in this mapping.

High-Level Language Tools for Reconfigurable Computing

“…The major research efforts in compiling high-level languages to reconfigurable computing are surveyed in [14]. The paper offers an in-depth analysis of the tools available at that time.…”

SAccO: An implementation platform for scalable FPGA accelerators

“…For the software implementation, the API functions are implemented with socket connections. 3 As an example, the software implementation of our main visualization application in the HPVis project is shown in Fig. 3(a).…”

“…Normally, this interface is connected to the data FIFOs to and from the user logic. 3 We chose a socket implementation for its simplicity over other options like MPI [8]. Furthermore, sockets also enable distributed implementations.…”

“…the lack of mature highlevel synthesis (HLS) methods, has been researched intensively [2,3], but no solutions mature enough for industrial applications are available yet. Therefore we do not use HLS systems nor automatic hardware/software partitioning methods (which require HLS) in this work.…”

Automated framework for FPGA-based parallel genetic algorithms

“…To simplify the design process, a streaming high-level synthesis tool Maxcompiler is used as an intermediate-level target [15], [16], [17], [18]. We will show how our proposed work addresses these problems in section III and IV.…”